Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 17, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed December 17, 2024 and May 30, 2025 have been
considered.
Claim Objections
Claims 2-11 and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 12205652 [‘652]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘652
1. A method for reading a memory device, wherein the memory device comprises a first word line, a second word line, and memory cells, the memory cells comprise first memory cells coupled to the first word line and second memory cells coupled to the second word line, each of the memory cells being configured to storing M bits data, and M is a positive integer greater than or equal to 2, the method comprising: applying at least one first voltage to the first word line; and after applying the at least one first voltage to the first word line, performing a read operation of reading a first level of 2M levels of the second memory cells, comprising: performing a first read operation based on a first condition; and performing a second read operation based on a second condition, wherein the first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.
1. A method for reading a memory device, wherein the memory device comprises a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, each of the multi-bit memory cells being configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages, the method comprising: reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell by using at least one sampling voltage; determining at least one offset flag, each representing a size of a respective one of at least one read offset according to a sampling read value of each of the at least one sampling voltage, wherein the at least one sampling voltage is at least one of the multi-level preset read voltages, the at least one sampling voltage comprises N sampling voltages, each of the multi-level preset read voltages corresponds to N+1 read offsets, and N is a positive integer greater than or equal to 2; and reading the to-be-read multi-bit memory cell, according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag.
12. The method of claim 1, wherein the first word line and the second word line are adjacent.
“…reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell…” – claim 1.
As can be seen from the above table, claim 1 of the application's step of "applying a voltage to a word-line" followed by "performing a read operation using a first condition and a second condition (differing in voltage or time)" is substantively identical to claim 1 of the patent ‘652's teaching of "reading an adjacent multi-bit memory cell" using "at least one sampling voltage" to determine "offset flags" and "read offsets" to accurately read the target cell. The patent discloses determining read offsets dynamically via sampling voltages (which inherently involves applying word-line voltages under different conditions, such as varying read voltages or sensing times, to establish offset flags). The application’s recitation of performing a read based on a "first condition" and "second condition" (comprising a voltage or a time) encompasses the exact iterative sampling and offset adjustment taught by the patent. The application merely uses alternative terminology ((2M) levels, first/second conditions) for what the reference defines as multi-level preset read voltages and (N) sampling voltages to determine read offsets. The structural and functional outcomes are identical. A difference in voltage or sensing time used to read multi-level memory cells represents an obvious optimization of read margins that does not define a separate, patentable invention over the base method of adjacent word-line sampling and offset adjustment. Therefore, coverage have already been given to the earlier filed patent application.
Claims 13 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10 of U.S. Patent No. 12205652 [‘652]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘652
13. A memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array comprises a first word line, a second word line, and memory cells, the memory cells comprise first memory cells coupled to the first word line and second memory cells coupled to the second word line, each of the memory cells being configured to storing M bits data, and M is a positive integer greater than or equal to 2; and the peripheral circuit is configured to: apply at least one first voltage to the first word line; and after applying the at least one first voltage to the first word line, perform a read operation of reading a first level of 2M levels of the second memory cells, comprising: perform a first read operation based on a first condition; and perform a second read operation based on a second condition, wherein the first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.
10. A memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array comprises a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines; and the peripheral circuit is configured to: read a stored value of each of the multi-bit memory cells through multi-level preset read voltages; read a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell by using at least one sampling voltage; determine at least one offset flag, each representing a size of a respective one of at least one read offset according to a sampling read value of each of the at least one sampling voltage; and read the to-be-read multi-bit memory cell, according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag, wherein the at least one sampling voltage is at least one of the multi-level preset read voltages, the at least one sampling voltage comprises N sampling voltages, each of the multi-level preset read voltages corresponds to N+1 read offsets, and N is a positive integer greater than or equal to 2.
20. The memory device of claim 13, wherein the first word line and the second word line are adjacent.
“…reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell…” – claim 10.
As can be seen from the above table, claim 13 of the application's step of "applying a voltage to a word-line" followed by "performing a read operation using a first condition and a second condition (differing in voltage or time)" is substantively identical to claim 10 of the patent ‘652's teaching of "reading an adjacent multi-bit memory cell" using "at least one sampling voltage" to determine "offset flags" and "read offsets" to accurately read the target cell. The patent discloses determining read offsets dynamically via sampling voltages (which inherently involves applying word-line voltages under different conditions, such as varying read voltages or sensing times, to establish offset flags). The application’s recitation of performing a read based on a "first condition" and "second condition" (comprising a voltage or a time) encompasses the exact iterative sampling and offset adjustment taught by the patent. The application merely uses alternative terminology ((2M) levels, first/second conditions) for what the reference defines as multi-level preset read voltages and (N) sampling voltages to determine read offsets. The structural and functional outcomes are identical. A difference in voltage or sensing time used to read multi-level memory cells represents an obvious optimization of read margins that does not define a separate, patentable invention over the base method of adjacent word-line sampling and offset adjustment. Therefore, coverage have already been given to the earlier filed patent application.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miccoli et al. [US Patent Application # 20190043565].
With respect to claim 1, Miccoli et al. disclose a method for reading a memory device, wherein the memory device [fig. 1] comprises a first word line [WL(N), a second word line [WL(N+1)], and memory cells [within 114], the memory cells comprise first memory cells [125’s] coupled to the first word line and second memory cells [126’s] coupled to the second word line, each of the memory cells being configured to storing M bits data, and M is a positive integer greater than or equal to 2 [“…receive a request to read data stored in a first memory cell of a multi-level non-volatile memory array, wherein the data includes at least 4 bits…” – par. 0059], the method comprising: applying at least one first voltage to the first word line [“receive read request for target memory cell” – 402 of fig. 4]; and after applying the at least one first voltage to the first word line, performing a read operation of reading a first level of 2M levels of the second memory cells [“read adjacent memory cell…” - 404 of fig. 4], comprising: performing a first read operation based on a first condition [406 “adjacent memory cell programming state – “>level 0: “programmed” – 412/414]; and performing a second read operation based on a second condition [“adjacent memory cell programming state” – “level 0: erased” – 412/408], wherein the first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.
With respect to claim 12, Miccoli et al. disclose the first word line and the second word line are adjacent. See figs. 1 and 5.
Claim(s) 13 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miccoli et al. [US Patent Application # 20190043565].
With respect to claim 13, Miccoli et al. disclose a memory device [fig. 1], comprising: a memory cell array [114] and a peripheral circuit [112] coupled to the memory cell array, wherein the memory cell array comprises a first word line [WL(N+1)], a second word line [WL(N)], and memory cells, the memory cells comprise first memory cells [126’S] coupled to the first word line and second memory cells [125’S] coupled to the second word line, each of the memory cells being configured to storing M bits data, and M is a positive integer greater than or equal to 2 [“…receive a request to read data stored in a first memory cell of a multi-level non-volatile memory array, wherein the data includes at least 4 bits…” – par. 0059]; and the peripheral circuit is configured to: apply at least one first voltage to the first word line [“receive read request for target memory cell” – 402 of fig. 4]; and after applying the at least one first voltage to the first word line, perform a read operation of reading a first level of 2M levels of the second memory cells [“read adjacent memory cell…” - 404 of fig. 4], comprising: perform a first read operation based on a first condition [“adjacent memory cell programming state – “>level 0: “programmed” – 412/414]; and perform a second read operation based on a second condition [“adjacent memory cell programming state” – “level 0: erased” – 412/408], wherein the first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.
With respect to claim 20, Miccoli et al. disclose the first word line and the second word line are adjacent. See figs. 1 and 5.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2: The method of claim 1, further comprising: applying a second voltage to the second word line during the first read operation; and applying a third voltage to the second word line during the second read operation, wherein the third voltage is a sum of the second voltage and a first offset, the first offset is based on a reading value of the first memory cells obtained by applying the at least one first voltage to the first word line.
-with respect to claim 14: The memory device of claim 13, wherein the peripheral circuit is further configured to: apply a second voltage to the second word line during the first read operation; and apply a third voltage to the second word line during the second read operation, wherein the third voltage is a sum of the second voltage and a first offset, and the first offset is based on a reading value of the first memory cells obtained by applying the at least one first voltage to the first word line.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 July 1, 2026
Prosecution Insights