DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 8/31/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of Patent 12211562 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Allowable Subject Matter
Claim 6-8, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 9 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: performing an erase operation of a memory device, the memory device comprising at least one memory block, the memory block comprising a first deck and a second deck, the method comprising: performing a first erase operation on the first deck; applying a first verification voltage to at least one first word line coupled to the first deck to verify the first erase operation; and performing a second erase operation on the second deck, wherein the first verification voltage is lower than a reference verification voltage, and the reference verification voltage is a voltage applied to the at least one first word line or at least one second word line coupled to the second deck during a verification operation to verify a full block erase operation for the first deck and the second deck, and a combination of other limitations in the independent claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, (PGPUB 20190019563), hereinafter as Lee.
Regarding claim 1, Lee teaches a method for performing an erase operation of a memory device, the memory device comprising at least one memory block, the memory block comprising a first deck and a second deck (Fig 1, memory block has different layers/decks, and [0029] vertical channel), the method comprising:
performing a first erase operation on the first deck (Fig 5, S130-S150);
applying a first verification voltage to at least one first word line coupled to the first deck to verify the first erase operation for the first deck (Fig 6, Fig 7 S350);
performing a second erase operation on the second deck (Lee does not expressly disclose separate erase operations, but mere duplication of the essential working parts of a device involves only routine skill in the art St. Regis Paper Co. v. Bemis Co., 193 USPQ8.); and
applying a second verification voltage to at least one second word line coupled to the second deck to verify the second erase operation, wherein the second verification voltage is different from the first verification voltage (Fig 7, S370).
Regarding claim 2, Lee teaches the second deck is between the first deck and a source line (Fig 3); and the first verification voltage is lower than the second verification voltage ([0060]).
Regarding claim 3/18, Lee teaches applying the first verification voltage to the at least one first word line comprises: apply the first verification voltage with a first voltage value to the at least one first word line, in response to memory cells coupled to the second deck being in a programming state; and
apply the first verification voltage with a second voltage value to the at least one first word line, in response to the memory cells coupled to the second deck being in an erasing state, wherein the first voltage value is greater than the second voltage value ([0056]).
Regarding claim 4, Lee teaches the memory block further comprises a third deck, and the method further comprises:
perform a third erase operation on the third deck; and
apply a third verification voltage to at least one third word line coupled to the third deck to verify the third erase operation, wherein the third verification voltage is different from the first verification voltage (mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
Regarding claim 16, Lee teaches memory device, comprising:
a memory array comprising at least one memory block, the memory block comprising a first deck coupled to at least one first word line and a second deck coupled to at least one second word line (Fig 1); and a peripheral circuit (Fig 1, peripheral circuit) coupled to the memory array and configured to:
performing a first erase operation on the first deck (Fig 5);
applying a first verification voltage to the at least one first word line to verify the first erase operation for the first deck (Fig 5-6, and Fig 7 S350);
performing a second erase operation on the second deck (case law used in rejection of claim 1 applies); and
applying a second verification voltage to the at least one second word line to verify the second erase operation, wherein the second verification voltage is different from the first verification voltage (Fig 7, S370).
Regarding claim 17, Lee teaches the first deck is between the second deck and a bit line, and the second deck is between the first deck and a source line (Fig 3); and the first verification voltage is lower than the second verification voltage (Fig 7 and [0060]).
Regarding claim 19, arguments used in rejection of claim 4 applies.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Liu et al. (PGPUB 20200075102), hereinafter as Liu.
Regarding claim 5, Lee teaches a method as in rejection of claim 4,
But not expressly the values of three verification voltages in an increasing order,
Liu teaches a third deck is between the first deck and the second deck, the first deck is between the third deck and a bit line, the second deck is between the third deck and a source line, and the first verification voltage is lower than the third verification voltage; and the third verification voltage is lower than the second verification voltage (Fig 6).
Since Liu and Lee are both from the same field of semiconductor memory device, the purpose disclosed by Liu would have been recognized in the pertinent art of Lee.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the verification voltages as in Liu into the device of Lee for the purpose of ensuring success erasing operation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827
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