DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12211562. Although the claims at issue are not identical, they are not patentably distinct from each other because at least independent claims is disclosed by claim 1 of 12211562:
Note: claim 7-8, claim 9-11, 13-14 are only rejected on the base of DP.
Instant app
12211562
PNG
media_image1.png
464
1064
media_image1.png
Greyscale
PNG
media_image2.png
316
466
media_image2.png
Greyscale
PNG
media_image3.png
330
1050
media_image3.png
Greyscale
Claim 9, 16, or 20
Claim 1
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3, 6, 12, 15, 18 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 3 states “in response to memory cells corresponding to the second deck being in a programming state.”: this is a contradict statement to what is in the relevant claims: in claim 1, an erase operation is operated on the second deck in the claims.
Claim 6, 12, 15 or 18 comprises similar 112 issue.
In the remaining of this office action, these clauses are not considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 16-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (PGPUB 20170271025), hereinafter as Suzuki.
Regarding claim 1, Suzuki teaches a method for performing an erase operation of a memory device, the memory device comprising at least one memory block, the memory block comprising a first deck and a second deck (Fig 3, memory block has different layers/decks), the method comprising:
performing a first erase operation on the first deck ([0074] an erase operation);
applying a first verification voltage to at least one first word line coupled to the first deck to verify the first erase operation for the first deck (Fig 7, zone 12 with Vverify12);
performing a second erase operation on the second deck (Suzuki does not expressly disclose separate erase operations, but mere duplication of the essential working parts of a device involves only routine skill in the art St. Regis Paper Co. v. Bemis Co., 193 USPQ8.); and
applying a second verification voltage to at least one second word line coupled to the second deck to verify the second erase operation, wherein the second verification voltage is different from the first verification voltage (Fig 7, zone 11 with Vverify11).
Regarding claim 2, Suzuki teaches the second deck is between the first deck and a source line; and the first verification voltage is lower than the second verification voltage (Fig 7 and Fig 3).
Regarding claim 3, Suzuki teaches applying the first verification voltage to the at least one first word line comprises: apply the first verification voltage with a first voltage value to the at least one first word line, in response to memory cells coupled to the second deck being in a programming state; and apply the first verification voltage with a second voltage value to the at least one first word line, in response to the memory cells coupled to the second deck being in an erasing state, wherein the first voltage value is greater than the second voltage value (Fig 4).
Regarding claim 4, Suzuki teaches the memory block further comprises a third deck, and the method further comprises:
perform a third erase operation on the third deck; and
apply a third verification voltage to at least one third word line coupled to the third deck to verify the third erase operation, wherein the third verification voltage is different from the first verification voltage (Fig 7, Verify10/11/12).
Regarding claim 16, Suzuki teaches memory device, comprising:
a memory array comprising at least one memory block, the memory block comprising a first deck coupled to at least one first word line and a second deck coupled to at least one second word line (Fig 3); and a peripheral circuit (Fig 1, peripheral circuit) coupled to the memory array and configured to:
performing a first erase operation on the first deck ([0074]);
applying a first verification voltage to the at least one first word line to verify the first erase operation for the first deck (Fig 7, zone 12 with Vverify12);
performing a second erase operation on the second deck (case law used in rejection of claim 1 applies); and
applying a second verification voltage to the at least one second word line to verify the second erase operation, wherein the second verification voltage is different from the first verification voltage (Fig 7, zone 11 with Vverify11).
Regarding claim 17, Suzuki teaches the first deck is between the second deck and a bit line, and the second deck is between the first deck and a source line; and the first verification voltage is lower than the second verification voltage (Fig 7 and Fig 3).
Regarding claim 19, arguments used in rejection of claim 4 applies.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, in view of Liu et al. (PGPUB 20200075102), hereinafter as Liu.
Regarding claim 5, Suzuki teaches a method as in rejection of claim 4,
But not expressly the values of three verification voltages in an increasing order,
Liu teaches a third deck is between the first deck and the second deck, the first deck is between the third deck and a bit line, the second deck is between the third deck and a source line, and the first verification voltage is lower than the third verification voltage; and the third verification voltage is lower than the second verification voltage (Fig 6).
Since Liu and Suzuki are both from the same field of semiconductor memory device, the purpose disclosed by Liu would have been recognized in the pertinent art of Suzuki.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the verification voltages as in Liu into the device of Suzuki for the purpose of ensuring success erasing operation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MIN HUANG/ Primary Examiner, Art Unit 2827
Prosecution Insights