Prosecution Insights
Last updated: July 17, 2026
Application No. 18/984,515

DUMMY DATA-BASED READ REFERENCE VOLTAGE SEARCH OF NAND MEMORY

Non-Final OA §102
Filed
Dec 17, 2024
Priority
Jan 09, 2023 — continuation of PCTCN2023071275 +1 more
Examiner
PHAM, LY D
Art Unit
Tech Center
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
970 granted / 1032 resolved
+34.0% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
24 currently pending
Career history
1046
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
34.1%
-5.9% vs TC avg
§102
36.5%
-3.5% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1032 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 20 of U.S. Patent No. 12,211,547. Although the claims at issue are not identical, they are not patentably distinct from each other because each and every limitation claimed herein has in fact been claimed and patented. Namely: Pending claim 1 corresponds to patented claim 1. Pending claim 2 corresponds to patented claim 2. Pending claim 3 corresponds to patented claim 4. Pending claim 4 corresponds to patented claims 3 and 5. Pending claim 5 corresponds to patented claim 6. Pending claim 6 corresponds to patented claim 9. Pending claim 7 corresponds to patented claim 10. Pending claim 8 corresponds to patented claim 12. Pending claim 9 corresponds to patented claim 11. Pending claim 10 corresponds to patented claim 17. Pending claim 11 corresponds to patented claim 17. Pending claim 12 corresponds to patented claims 18 and 19. Pending claim 13 corresponds to patented claim 12. Pending claim 14 corresponds to patented claim 20. Pending claim 15 corresponds to patented claim 20. Pending claim 16 corresponds to patented claim 2. Pending claim 17 corresponds to patented claim 4. Pending claim 18 corresponds to patented claim 6. Pending claim 19 corresponds to patented claim 12. Pending claim 20 corresponds to patented claim 11. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 6, 8, 10, 13, 14, and 19 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Muzzetto et al. (US Pat Pub 2022/0319618). Regarding claims 1, 10 and 14, Muzzetto et al. disclose a memory system/method (for example figs. 1 – 10 and all related texts), comprising: memory device (100, fig. 1, including memory cells array 100’, fig. 1); memory controller (referred to as circuitry 142 that writes to and reads from the memory cell 100’, fig. 1, para 0021), configured to: perform a single-read operation with a read reference voltage (reference voltage, para 0031, 0054) having a first level on a set of memory cells in a memory device to obtain first bits (referred to as read voltage to first group of memory cells corresponding to a preset number of memory cells, see abstract and para 0031, 0032, 0043); determine second bits corresponding to the set of memory cells (referred to in abstract as “additional information” that is based on to determine the voltage difference, which is the determined/computed second threshold voltage for the memory cells programmed to a first logic state. See abstract), the second bits corresponding to data being initially programmed into the set of memory cell (referred to in abstract as “memory cells PROGRMMAED to the first logic state”); and determine a read voltage based on the first bits and the second bits (read voltage determined based on the additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to the first logic state. See abstract and para 0043. See also para 0141, 0144). Regarding claim 6, Muzzetto et al. also disclose the method as set forth in claim 1, wherein the method is triggered in response to an error correction code (ECC) decoding fails (see para 0071). Regarding claims 8, 13 and 19, Muzzetto et al. also disclose the method of claim 1, wherein the first bits and the second bits both correspond to dummy data; and the dummy data is one of: data of codewords that belong to multiple pages that are stored in a horizontal memory cell string including the set of memory cells associated with a word line, and data of multiple pages that are stored in a horizontal memory cell string including the set of memory cells associated with a word line (referred to in para 0042 – 0050, etc…). Allowable Subject Matter Claims 2 – 5, 7, 9, 11, 12, 15 – 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (and the Double Patenting Rejection in paragraph 3 above is overcome). The following is a statement of reasons for the indication of allowable subject matter: The prior arts of record fail to teach or reasonably suggest the memory system/method set as forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 2, 7, 9, 11, 15, and 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LY D. PHAM Examiner Art Unit 2827 /LY D PHAM/Primary Examiner, Art Unit 2827 June 24, 2026
Read full office action

Prosecution Timeline

Dec 17, 2024
Application Filed
Jul 02, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.3%)
1y 8m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1032 resolved cases by this examiner. Grant probability derived from career allowance rate.

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