Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 30th, 2026 has been entered. Claims 1-16 are pending in this application. Independent claims 1 and 7 were amended to further teach performing the soft page offline operation on the to-be-offlined address without releasing a mirror relationship between the first and second memory, wherein the first memory, except the fault address, can still support read and write.
Applicant’s amendments to the claims have been fully considered. However, upon further consideration of the amended claims, a new ground(s) of rejection is made, as set forth below.
Response to Arguments
Applicant's arguments filed June 30th, 2026 have been fully considered but they are not persuasive. Applicant argues that Zhou et al. (US 2022/0350715), hereinafter Zhou, teaching of runtime failover from a faulty memory region to a spare memory region does not teach the claimed soft page offline operation. Examiner ahs considered Applicant’s argument and has modified the rejection as set forth below. Dong et al. (US 9,336,036), hereinafter Dong, teaches offlining or disabling a corrupted memory page and allocating a replacement memory page. Dong also teaches restoring the corrupted page from corresponding mirroring memory and continuing execution following the page-level recovery. Accordingly, the rejection no longer relies on Zhou’s runtime failover disclosure alone for reaching the claimed soft page offline operation.
Regarding the newly added limitation, Dong further teaches maintaining the use of the mirroring memory during the page offlining and recovery process. After the corrupted page is offlined, the corresponding memory page is used to restore the guest memory page’s contents, and then execution continues. Therefore, Dong teaches the amended limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 7-8, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Dong, in view of Zhou.
Regarding claim 1, Dong teaches a method for processing a memory fault (Dong, Abstract teaches recovering from memory failure using guest memory and corresponding mirroring memory; upon memory failure, a corrupted page is identified, recovered from the mirror memory, and execution continues), comprising:
obtaining first target data corresponding to the fault address from a second memory (Dong, col. 13, lines 13-27 teaches determining the corresponding mirroring host page for the corrupted guest memory page and restores the guest memory page contents from the mirroring page), and writing the first target data into the fault address in the first memory (Dong, col. 13, lines 13-27 teaches copying contents from the mirroring page to the new memory page to restore the corrupted guest memory page), wherein the first memory and the second memory are mutual mirrored memories, wherein the first memory and the second memory are mutual mirrored memories (Dong, col. 7, lines 42-53 & col. 9, lines 8-39 teach mirroring pages that mirror the original mapped physical page, including 1 to 1 mirroring, and maintains the mapping relationship; it also teaches writing the same content to the original and corresponding mirror addresses);
examining second target data at the fault address in the first memory (Dong, col. 10, lines 1-7 teaches modifying translated code to compare the contents in the original guest memory and mirroring memory addresses after executing the memory write instructions to verify that the writes were executed correctly), and if the second target data is determined as fault data (Dong, col. 10, lines 1-7 teaches verifying the written contents by comparison & col. 11, lines 30-38 teaches identifying a corrupted page based on error information such as the error physical address); and
performing a soft page offline operation on the to-be-offlined address (Dong, col. 11, lines 35-38 & col. 13, lines 8-12 teach the VMM may offline or disable the corrupted memory page and allocate a replacement) without releasing a mirror relationship between the first memory and the second memory (Dong, col. 13, lines 13-48 teaches that after offlining the corrupted page, the corresponding page is used to restore the guest memory page and continuing execution), wherein the first memory except the fault address can still support read and write (Dong, col. 13, lines 49-67 through col. 14, lines 1-44 teaches performing recovery on specific pages and then continuing execution of subsequent translated codes and the guest OS; it also teaches continuing operation after localized recovery).
Dong fails to teach obtaining uncorrectable error information of a first memory, wherein the uncorrectable error information comprises a fault address, and marking the fault address in the first memory as a to-be-offlined address.
However, Zhou, in an analogous art, teaches obtaining uncorrectable error information of a first memory (Zhou, para. [0042] teaches obtaining uncorrectable error information of a memory, where error information is provided to controller 140 indicating detection of correctable errors [CE] and uncorrectable errors [UE] and indicating when & where the errors occurred), wherein the uncorrectable error information comprises a fault address (Zhou, para. [0072]-[0073] & [0096]-[0098] teaches that the error information identifies a fault address, wherein fault addressees are stored and defective memory regions are identified using row and column address information), and marking the fault address in the first memory as a to-be-offlined address (Zhou, Fig. 2B teaches a region directory 264 and cacheline sparing directory 270, which corresponds to marking faulty memory addresses or regions for replacement or offlining).
Dong and Zhou are both considered to be analogous to the claimed invention because both are in the same field of failure recovery in memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Dong to incorporate the teachings of Zhou by including the functionality of uncorrectable error analysis and faulty address tracking.
The suggestion/motivation for doing so would be to more precisely identify memory locations associated with uncorrectable errors to help with targeted recovery and localized page offlining, while maintaining operation of the mirrored memory system.
Regarding claim 2, the combination of Dong in view of Zhou teaches the method according to claim 1, wherein the marking the fault address in the first memory as the to-be-offlined address comprises: marking the fault address in the first memory as the to-be-offlined address based on a to-be-offlined identification (Zhou, Fig. 2B, region directory 264; Fig. 1, sparing region 136; an entry made to the region directory or the sparing region equates to to-be off lined identification).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Dong to incorporate the teachings of Zhou by including the functionality of marking memory locations based on identification.
The suggestion/motivation for doing so would be to facilitate targeted offlining or identified faulty memory locations.
Regarding claim 3, the combination of Dong in view of Zhou teaches the method according to claim 1, wherein the performing the soft page offline operation on the to-be-offlined address comprises: performing the soft page offline operation on the to-be-offlined address by using an operating system(OS) (Zhou, Fig. 1, OS 114). Zhou teaches an OS being part of the system that manages memory and interacts with memory fault handling and sparing/failover operations.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Dong to incorporate the teachings of Zhou by including the functionality of using an OS for page offline operations.
The suggestion/motivation for doing so would be to allow for isolation of faulty memory regions.
Regarding claim 7, Dong teaches a computing device (Dong, Fig. 1, processor-based platform 116), comprising:
a processor (Dong, Fig. 1, processor 126 or platform hardware 116),
a first memory (Dong, Fig. 1, memory 120),
a second memory, wherein the first memory and the second memory are mutual mirrored memories (Dong, col. 7, lines 42-53 & col. 9, lines 8-39 teach mirroring pages that mirror the original mapped physical page, including 1 to 1 mirroring, and maintains the mapping relationship; it also teaches writing the same content to the original and corresponding mirror addresses), and
wherein
the memory controller is configured to:
obtain first target data corresponding to the fault address from a second memory (Dong, col. 13, lines 13-27 teaches determining the corresponding mirroring host page for the corrupted guest memory page and restores the guest memory page contents from the mirroring page), and write the first target data into the fault address in the first memory (Dong, col. 13, lines 13-27 teaches copying contents from the mirroring page to the new memory page to restore the corrupted guest memory page);
examine second target data at the fault address in the first memory (Dong, col. 10, lines 1-7 teaches modifying translated code to compare the contents in the original guest memory and mirroring memory addresses after executing the memory write instructions to verify that the writes were executed correctly);
the processor is configured to:
determine if the second target data is determined as fault data (Dong, col. 10, lines 1-7 teaches verifying the written contents by comparison & col. 11, lines 30-38 teaches identifying a corrupted page based on error information such as the error physical address); and
perform a soft page offline operation on the to-be-offlined address (Dong, col. 11, lines 35-38 & col. 13, lines 8-12 teach the VMM may offline or disable the corrupted memory page and allocate a replacement) without releasing a mirror relationship between the first memory and the second memory (Dong, col. 13, lines 13-48 teaches that after offlining the corrupted page, the corresponding page is used to restore the guest memory page and continuing execution), wherein the first memory except the fault address can still support read and write (Dong, col. 13, lines 49-67 through col. 14, lines 1-44 teaches performing recovery on specific pages and then continuing execution of subsequent translated codes and the guest OS; it also teaches continuing operation after localized recovery).
Dong fails to teach a memory controller coupled to the processor, the first memory, and the second memory, obtain uncorrectable error information of a first memory, wherein the uncorrectable error information comprises a fault address, and mark the fault address in the first memory as a to-be-offlined address.
However, Zhou, in an analogous art, teaches a memory controller coupled to the processor, the first memory, and the second memory (Zhou, Fig. 1, memory controller 116 and/or controller 122), obtain uncorrectable error information of a first memory (Zhou, para. [0042] teaches obtaining uncorrectable error information of a memory, where error information is provided to controller 140 indicating detection of correctable errors [CE] and uncorrectable errors [UE] and indicating when & where the errors occurred), wherein the uncorrectable error information comprises a fault address (Zhou, para. [0072]-[0073] & [0096]-[0098] teaches that the error information identifies a fault address, wherein fault addressees are stored and defective memory regions are identified using row and column address information), and mark the fault address in the first memory as a to-be-offlined address (Zhou, Fig. 2B teaches a region directory 264 and cacheline sparing directory 270, which corresponds to marking faulty memory addresses or regions for replacement or offlining).
Dong and Zhou are both considered to be analogous to the claimed invention because both are in the same field of failure recovery in memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Dong to incorporate the teachings of Zhou by including the functionality of uncorrectable error analysis and faulty address tracking, as well as using a memory controller coupled to the processor and memories.
The suggestion/motivation for doing so would be to more precisely identify memory locations associated with uncorrectable errors to help with targeted recovery and localized page offlining, while maintaining operation of the mirrored memory system, as well as providing centralized control of error/fault management operations.
Claim 8 is a computing device with limitations similar to the method of claim 2, and is rejected under the same rationale.
Claim 11 is a non-transitory machine-readable storage medium with limitations similar to the method of claim 1, and is rejected under the same rationale.
Claim 12 is a non-transitory machine-readable storage medium with limitations similar to the method of claim 2, and is rejected under the same rationale.
Claim 13 is a non-transitory machine-readable storage medium with limitations similar to the method of claim 3, and is rejected under the same rationale.
Claims 4-6, 9-10, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Dong in view of Zhou, as applied to claim 3 above, and further in view of Dell et al. (US 10,209,896), hereinafter Dell.
Regarding claim 4, the combination of Dong in view of Zhou teaches the method according to claim 3, but fails to teach wherein the marking the fault address in the first memory as the to-be-offlined address based on the to-be-offlined identification comprises: generating a generic hardware error source (GHES) table, wherein the GHES table comprises the fault address and the corresponding to-be-offlined identification.
However, Dell, in an analogous art, teaches wherein the marking the fault address in the first memory as the to-be-offlined address based on the to-be-offlined identification comprises: generating a generic hardware error source (GHES) table, wherein the GHES table comprises the fault address and the corresponding to-be-offlined identification (Dell, col. 4, lines 26-31, “In an embodiment, the memory controller 202 stores a fault management table [FMT] 214 for tracking memory failure events identified by the ECC units 212A and 212B, e.g., symbol marks and/or chip marks in a memory array or buffer”).
Dong, Zhou, and Dell are considered to be analogous to the claimed invention because they are in the same field of failure recovery in memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Dong in view of Zhou, to incorporate the teachings of Dell by including the functionality of having a fault management table.
The suggestion/motivation for doing so would be to maintain information identifying memory failure events and their corresponding memory locations, which allows for tracking and management of memory faults.
Regarding claim 5, the combination of Dong in view of Zhou, further in view of Dell teaches the method according to claim 4, wherein a fault level of the fault address in the GHRES table is correctable (Zhou teaches determining/classifying memory faults as correctable & uncorrectable errors, and Dell teaches a fault management table [FMT]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Dong in view of Zhou, to incorporate the teachings of Dell by including the functionality of having a fault management table that stores correctable errors.
The suggestion/motivation for doing so would be to identify the type of memory fault and allow for selecting the appropriate fault recovery/management operation.
Regarding claim 6, the combination of Dong in view of Zhou, further in view of Dell teaches the method according to claim 5, wherein the performing the soft page offline operation on the to-be-offlined address comprises: performing, by using the OS (Zhou, Fig. 1, OS 114), the soft page offline operation on the fault address corresponding to the to-be-offlined identification (Zhou, Fig. 2B, region directory 264; Fig. 1, sparing region 136; an entry made to the region directory or the sparing region equates to to-be off lined identification) and whose fault level is correctable in the GHES table (Zhou teaches correctable & uncorrectable errors, and Dell teaches a fault management table [FMT]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Dong in view of Zhou, to incorporate the teachings of Dell by including the functionality of using a fault management table and to-be-offlined identification, to perform page offlining operation.
The suggestion/motivation for doing so would be to identify offline memory locations based on fault information, while allowing for continued operation of unaffected memory.
Claim 9 is a computing device with limitations similar to the method of claim 4, and is rejected under the same rationale.
Claim 10 is a computing device with limitations similar to the method of claim 6, and is rejected under the same rationale.
Claim 14 is a non-transitory machine-readable storage medium with limitations similar to the method of claim 4, and is rejected under the same rationale.
Claim 15 is a non-transitory machine-readable storage medium with limitations similar to the method of claim 5, and is rejected under the same rationale.
Claim 16 is a non-transitory machine-readable storage medium with limitations similar to the method of claim 6, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gim et al. (US 12,019,503) teaches offlining faulty memory pages while continuing to use unaffected memory .
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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