Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 12/17/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/09/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2, 7, 11, 12, 13, 17, 19, and 20 are objected to because of the following informalities:
Regarding claim 2, in line 2-3, “based on the operation condition” appears that it should read as “based on the operating condition”.
Regarding claim 7, in line 2-5, “comprises the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage” appears that it should read as “comprises a first condition in which the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and a second condition in which the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage”.
Regarding claim 11, in line 2-3, “wherein the pre-change switch system” appears that it should read as “wherein the pre-charge switch system”.
Regarding claim 12, in line 9, “a locked state with an AC gird voltage” appears that it should read as “a locked state with an AC grid voltage”;in line 10, “the locked state with the AC gird voltage” appears that it should read as “the locked state with the AC grid voltage”.
Regarding claim 13, in line 3-4, “based on the operation condition” appears that it should read as “based on the operating condition”.
Regarding claim 17, in line 5-6, “the locked state with the AC gird voltage” appears that it should read as “the locked state with the AC grid voltage”.in line 2-5, “comprises the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage” appears that it should read as “comprises a first condition in which the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and a second condition in which the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage”.
Regarding claim 19, in line 6, “the locked state with the AC gird voltage” appears that it should read as “the locked state with the AC grid voltage”.
Regarding claim 20, in line 8, “a locked state with an AC gird voltage” appears that it should read as “a locked state with an AC grid voltage”;in line 9, “the locked state with the AC gird voltage” appears that it should read as “the locked state with the AC grid voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, the limitation “within the current limit based on the control variables” recites “the control variables”, which lacks antecedent basis. Claim 3 depends from claim 1; however, the control variables are first introduced in claim 2. It is unclear whether claim 3 was intended to depend from claim 2. For purposes of examination, claim 3 is interpreted as depending from claim 2.
Regarding claim 14, the limitation “within the current limit based on the control variables” recites “the control variables”, which lacks antecedent basis. Claim 14 depends from claim 12; however, the control variables are first introduced in claim 13. For purposes of examination, claim 14 is interpreted as depending from claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 5, 10, 12, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pugliese (S. Pugliese et al., “Soft-Start Procedure for a Three-Stage Smart Transformer Based on Dual-Active Bridge and Cascaded H-Bridge Converters,” IEEE Transactions on Power Electronics, vol. 35, no. 10, pp. 11039-11052, October 2020) in view of Tafti (H. Dehghani Tafti et al., “Control of Active Front-End Rectifier of the Solid-State Transformer with Improved Dynamic Performance during Precharging,” 2017 IEEE Asian Conference on Energy, Power and Transportation Electrification (ACEPT), 2017) and further in view of Ahmed et al. (US Patent Application Publication US 2020/0119738 A1, hereinafter “Ahmed”).
Regarding claim 1, Pugliese discloses (see Fig. 1, Fig. 4, and Fig. 5) a method implemented by a computer system (see Fig. 4a and Fig. 6, the control system of the three-stage smart transformer), comprising: receiving DC bus voltage conditions of a plurality of AC to DC converters (the H-bridge cells of the cascaded H-bridge converter, each cell rectifying a portion of the AC input) of an Input-Series-Output-Parallel (ISOP) power converter (see Fig. 1 and Fig. 5, the CHB cells are connected in series at the MV AC side while the outputs of the DAB converters are connected in parallel at the LV DC side) during a rectification stage for pre-charging DC bus of the plurality of AC to DC converters (see Section II.C: “the MV dc-link capacitors are charged with the CHB acting as a passive rectifier”; see Section IV.A and Fig. 13, the DC-link voltages VDC,1 and VDC,2 are monitored during the pre-charging, where “the steady-state voltage values in the dc-links are different”); enabling a first voltage regulation to charge an AC to DC output of each of the plurality of AC to DC converters to reach a first reference voltage (see Section IV.D: “the CHB converter switches from passive rectifier to active rectifier operation and the total MV voltage control can be achieved”); determining an operating condition of the ISOP power converter, wherein the operating condition comprises (1) a load condition (see Fig. 13 and Section IV.B: “the system is in no-load operation and Ro is connected but not energized”; see Section IV.F describing the procedure at light-load operation versus rated load operation) and an output voltage condition associated with a plurality of Dual Active Bridge (DAB) converters (see Section II.B and Fig. 3, the LV dc-link capacitor is phase-shift controlled “from a zero initial voltage”; see Section IV.B: “The transferred power precharges the output capacitor up to a voltage value, which depends on the input voltage value”), and (2) a monitored voltage condition of each of the plurality of AC to DC converters (see Fig. 6 and Fig. 7, the DC-link voltage VDC,i of each cell is measured for the voltage balance control); enabling a second voltage regulation of each of the plurality of DAB converters to charge a DAB output to reach a second reference voltage within a current limit based on the operating condition (see Section IV.C, the DAB converters are activated controlling the output voltage Vo to the reference of Eq. (29); see Section V: “The output voltage reference is set to be equal to the instantaneous average value of the measured MV dc-link voltages”; see Section IV.B.2, where the duty-cycle slope is set considering the power modules maximum peak current, the input voltage VDC,i, and the start-up time constraint; see Fig. 15: “the current in each DAB is inside the safe operating area”); and maintaining the second reference voltage for the output voltage condition (see Section IV.D: “When the nominal steady-state MV dc-link voltage is reached, the output voltage reference Vo* is set to its nominal value”).
Pugliese does not disclose detecting (1) a peak voltage of each of the DC bus of the plurality of AC to DC converters during the rectification stage has reached a first threshold voltage, and (2) that a Phase Loop Lock (PLL) signal indicates a locked state with an AC grid voltage, and enabling the first voltage regulation upon the detection.
However, Tafti teaches (see Fig. 2, Fig. 3, and Fig. 4) detecting a peak voltage of the DC bus during a rectification stage has reached a first threshold voltage (see Fig. 3, the decision block “Vdc >= V1” evaluated during the passive precharging in which the converter operates as a passive diode rectifier through the precharging resistor; see Section III.A: “A threshold voltage value of V1 is set for the dc-link voltage, in which the operation mode changes from the passive precharging to active precharging mode”), and enabling a voltage regulation to charge the AC to DC output to reach a reference voltage upon the detection (see Fig. 4 and Section III.A, the converter switching is enabled and “it linearly increases from V1 to its nominal reference value (V2)”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese to include detecting that the peak voltage of each of the DC bus has reached a first threshold voltage during the rectification stage and enabling the first voltage regulation upon the detection, as taught by Tafti, because it can limit the inrush current of the active front-end rectifier during the start-up process to its nominal current (see Abstract and Section III.A of Tafti).
The combination of Pugliese and Tafti does not disclose detecting that a PLL signal indicates a locked state with an AC grid voltage and enabling the first voltage regulation upon detecting the locked state (Tafti computes the grid voltage angle using a PLL, see Fig. 5 and Section III.B of Tafti, but does not explicitly disclose detecting the locked state as a condition for enabling the regulation).
However, Ahmed teaches (see Fig. 4) detecting whether a PLL signal indicates a locked state of synchronization with an AC grid voltage (see [0029] of Ahmed, the power converter operates in “a first phase locked loop (PLL) control mode 206 that establishes a state of synchronization with the electric grid 102”; see [0032] of Ahmed, “detecting a loss of the state of synchronization with the electric grid”), operating the converter in a diode rectification mode when the converter is not synchronized (see [0033] of Ahmed, “switching the converter to a diode mode of operation using a set of anti-parallel diodes, by blocking the converter pulses”), and enabling the closed-loop converter regulation upon detecting that the state of synchronization is established (see [0036] of Ahmed, “re-establishing the state of synchronization and initiating re-charge of the dc-link capacitors by restoring the normal converter control scheme”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti to include detecting that the PLL signal indicates the locked state with the AC grid voltage and enabling the first voltage regulation upon the detection, as taught by Ahmed, because it can prevent converter tripping caused by a synchronization error between the converter and the grid and allows the converter to resume normal regulated operation in a faster timeframe (see [0009] of Ahmed, “the converter resumes normal operation once synchronization is re-established, and normal operation of the grid is therefore re-enabled in a faster timeframe”).
Regarding claim 4, Pugliese discloses (see Fig. 13) wherein the load condition comprises a no-load condition (see Fig. 13 and Section IV.B: “the system is in no-load operation and Ro is connected but not energized”; see Section IV.A, no loads are connected to the MV DC-links during the first step) and a partial load condition (see Section IV.F, where “light-load operation persists during all the soft-start period”, emulated with an output load of 10 kΩ as compared to the rated load of 32 Ω).
Regarding claim 5, Pugliese discloses (see Fig. 3) wherein the output voltage condition comprises a zero-output voltage condition (see Section II.B and Fig. 3, the LV dc-link capacitor is phase-shift controlled “from a zero initial voltage”) and a partial output voltage condition (see Section IV.B: “The transferred power precharges the output capacitor up to a voltage value, which depends on the input voltage value”, from which the closed-loop output voltage control of Section IV.C proceeds).
Regarding claim 10, Pugliese discloses (see Fig. 6) wherein the maintaining the second reference voltage for the output voltage condition comprises at least one of enabling an AC to DC voltage regulation (see Section IV.D, the CHB converter operates as an active rectifier controlling the total MV DC-link voltage), or enabling a DC to DC voltage regulation (see Section IV.C and Fig. 6, the DAB converters control the output voltage through a PI controller).
Regarding claim 12, Pugliese discloses (see Fig. 1, Fig. 4, and Fig. 5) a control system (see Fig. 4a and Fig. 6, the control system of the three-stage smart transformer) that performs operations comprising: receiving DC bus voltage conditions of a plurality of AC to DC converters (the H-bridge cells of the cascaded H-bridge converter, each cell rectifying a portion of the AC input) of an Input-Series-Output-Parallel (ISOP) power converter (see Fig. 1 and Fig. 5, the CHB cells are connected in series at the MV AC side while the outputs of the DAB converters are connected in parallel at the LV DC side) during a rectification stage for pre-charging DC bus of the plurality of AC to DC converters (see Section II.C: “the MV dc-link capacitors are charged with the CHB acting as a passive rectifier”; see Section IV.A and Fig. 13, the DC-link voltages VDC,1 and VDC,2 are monitored during the pre-charging, where “the steady-state voltage values in the dc-links are different”); enabling a first voltage regulation to charge an AC to DC output of each of the plurality of AC to DC converters to reach a first reference voltage (see Section IV.D: “the CHB converter switches from passive rectifier to active rectifier operation and the total MV voltage control can be achieved”); determining an operating condition of the ISOP power converter, wherein the operating condition comprises (1) a load condition (see Fig. 13 and Section IV.B: “the system is in no-load operation and Ro is connected but not energized”; see Section IV.F describing the procedure at light-load operation versus rated load operation) and an output voltage condition associated with a plurality of Dual Active Bridge (DAB) converters (see Section II.B and Fig. 3, the LV dc-link capacitor is phase-shift controlled “from a zero initial voltage”; see Section IV.B: “The transferred power precharges the output capacitor up to a voltage value, which depends on the input voltage value”), and (2) a monitored voltage condition of each of the plurality of AC to DC converters (see Fig. 6 and Fig. 7, the DC-link voltage VDC,i of each cell is measured for the voltage balance control); enabling a second voltage regulation of each of the plurality of DAB converters to charge a DAB output to reach a second reference voltage within a current limit based on the operating condition (see Section IV.C, the DAB converters are activated controlling the output voltage Vo to the reference of Eq. (29); see Section V: “The output voltage reference is set to be equal to the instantaneous average value of the measured MV dc-link voltages”; see Section IV.B.2, where the duty-cycle slope is set considering the power modules maximum peak current, the input voltage VDC,i, and the start-up time constraint; see Fig. 15: “the current in each DAB is inside the safe operating area”); and maintaining the second reference voltage for the output voltage condition (see Section IV.D: “When the nominal steady-state MV dc-link voltage is reached, the output voltage reference Vo* is set to its nominal value”).
Pugliese does not disclose detecting (1) a peak voltage of each of the DC bus of the plurality of AC to DC converters during the rectification stage has reached a first threshold voltage, and (2) that a Phase Loop Lock (PLL) signal indicates a locked state with an AC grid voltage, and enabling the first voltage regulation upon the detection.
However, Tafti teaches (see Fig. 2, Fig. 3, and Fig. 4) detecting a peak voltage of the DC bus during a rectification stage has reached a first threshold voltage (see Fig. 3, the decision block “Vdc >= V1” evaluated during the passive precharging in which the converter operates as a passive diode rectifier through the precharging resistor; see Section III.A: “A threshold voltage value of V1 is set for the dc-link voltage, in which the operation mode changes from the passive precharging to active precharging mode”), and enabling a voltage regulation to charge the AC to DC output to reach a reference voltage upon the detection (see Fig. 4 and Section III.A, the converter switching is enabled and “it linearly increases from V1 to its nominal reference value (V2)”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Pugliese to include detecting that the peak voltage of each of the DC bus has reached a first threshold voltage during the rectification stage and enabling the first voltage regulation upon the detection, as taught by Tafti, because it can limit the inrush current of the active front-end rectifier during the start-up process to its nominal current (see Abstract and Section III.A of Tafti). The combination of Pugliese and Tafti does not disclose detecting that a PLL signal indicates a locked state with an AC grid voltage and enabling the first voltage regulation upon detecting the locked state (Tafti computes the grid voltage angle using a PLL, see Fig. 5 and Section III.B of Tafti, but does not explicitly disclose detecting the locked state as a condition for enabling the regulation).
However, Ahmed teaches (see Fig. 4) detecting whether a PLL signal indicates a locked state of synchronization with an AC grid voltage (see [0029] of Ahmed, the power converter operates in “a first phase locked loop (PLL) control mode 206 that establishes a state of synchronization with the electric grid 102”; see [0032] of Ahmed, “detecting a loss of the state of synchronization with the electric grid”), operating the converter in a diode rectification mode when the converter is not synchronized (see [0033] of Ahmed, “switching the converter to a diode mode of operation using a set of anti-parallel diodes, by blocking the converter pulses”), and enabling the closed-loop converter regulation upon detecting that the state of synchronization is established (see [0036] of Ahmed, “re-establishing the state of synchronization and initiating re-charge of the dc-link capacitors by restoring the normal converter control scheme”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Pugliese as modified in view of Tafti to include detecting that the PLL signal indicates the locked state with the AC grid voltage and enabling the first voltage regulation upon the detection, as taught by Ahmed, because it can prevent converter tripping caused by a synchronization error between the converter and the grid and allows the converter to resume normal regulated operation in a faster timeframe (see [0009] of Ahmed, “the converter resumes normal operation once synchronization is re-established, and normal operation of the grid is therefore re-enabled in a faster timeframe”).
The combination of Pugliese and Tafti does not disclose one or more processors and a non-transitory memory coupled to the processors comprising instructions executable by the processors.
However, Ahmed teaches (see Fig. 1) a power converter control module comprising one or more processors and a non-transitory memory comprising instructions executable by the processors to perform the converter control operations (see [0016] of Ahmed, the power converter control module includes a processor and a memory storing instructions executable in the processor; see [0020] of Ahmed: “a processor and a non-transient memory storing instructions executable in the processor to control functioning and response of power converter 101”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Pugliese as modified in view of Tafti to include one or more processors and a non-transitory memory comprising instructions executable by the processors, as taught by Ahmed, because it can implement the converter control functions as encoded software instructions executable in a processor.
Regarding claim 15, Pugliese discloses (see Fig. 13) wherein the load condition comprises a no-load condition (see Fig. 13 and Section IV.B: “the system is in no-load operation and Ro is connected but not energized”; see Section IV.A, no loads are connected to the MV DC-links during the first step) and a partial load condition (see Section IV.F, where “light-load operation persists during all the soft-start period”, emulated with an output load of 10 kΩ as compared to the rated load of 32 Ω).
Regarding claim 16, Pugliese discloses (see Fig. 3) wherein the output voltage condition comprises a zero-output voltage condition (see Section II.B and Fig. 3, the LV dc-link capacitor is phase-shift controlled “from a zero initial voltage”) and a partial output voltage condition (see Section IV.B: “The transferred power precharges the output capacitor up to a voltage value, which depends on the input voltage value”, from which the closed-loop output voltage control of Section IV.C proceeds).
Regarding claim 20, Pugliese discloses (see Fig. 1, Fig. 4, and Fig. 5) operations performed by a control system of the three-stage smart transformer (see Fig. 4a and Fig. 6) comprising: receiving DC bus voltage conditions of a plurality of AC to DC converters (the H-bridge cells of the cascaded H-bridge converter, each cell rectifying a portion of the AC input) of an Input-Series-Output-Parallel (ISOP) power converter (see Fig. 1 and Fig. 5, the CHB cells are connected in series at the MV AC side while the outputs of the DAB converters are connected in parallel at the LV DC side) during a rectification stage for pre-charging DC bus of the plurality of AC to DC converters (see Section II.C: “the MV dc-link capacitors are charged with the CHB acting as a passive rectifier”; see Section IV.A and Fig. 13, the DC-link voltages VDC,1 and VDC,2 are monitored during the pre-charging, where “the steady-state voltage values in the dc-links are different”); enabling a first voltage regulation to charge an AC to DC output of each of the plurality of AC to DC converters to reach a first reference voltage (see Section IV.D: “the CHB converter switches from passive rectifier to active rectifier operation and the total MV voltage control can be achieved”); determining an operating condition of the ISOP power converter, wherein the operating condition comprises (1) a load condition (see Fig. 13 and Section IV.B: “the system is in no-load operation and Ro is connected but not energized”; see Section IV.F describing the procedure at light-load operation versus rated load operation) and an output voltage condition associated with a plurality of Dual Active Bridge (DAB) converters (see Section II.B and Fig. 3, the LV dc-link capacitor is phase-shift controlled “from a zero initial voltage”; see Section IV.B: “The transferred power precharges the output capacitor up to a voltage value, which depends on the input voltage value”), and (2) a monitored voltage condition of each of the plurality of AC to DC converters (see Fig. 6 and Fig. 7, the DC-link voltage VDC,i of each cell is measured for the voltage balance control); enabling a second voltage regulation of each of the plurality of DAB converters to charge a DAB output to reach a second reference voltage within a current limit based on the operating condition (see Section IV.C, the DAB converters are activated controlling the output voltage Vo to the reference of Eq. (29); see Section V: “The output voltage reference is set to be equal to the instantaneous average value of the measured MV dc-link voltages”; see Section IV.B.2, where the duty-cycle slope is set considering the power modules maximum peak current, the input voltage VDC,i, and the start-up time constraint; see Fig. 15: “the current in each DAB is inside the safe operating area”); and maintaining the second reference voltage for the output voltage condition (see Section IV.D: “When the nominal steady-state MV dc-link voltage is reached, the output voltage reference Vo* is set to its nominal value”).
Pugliese does not disclose detecting (1) a peak voltage of each of the DC bus of the plurality of AC to DC converters during the rectification stage has reached a first threshold voltage, and (2) that a Phase Loop Lock (PLL) signal indicates a locked state with an AC grid voltage, and enabling the first voltage regulation upon the detection.
However, Tafti teaches (see Fig. 2, Fig. 3, and Fig. 4) detecting a peak voltage of the DC bus during a rectification stage has reached a first threshold voltage (see Fig. 3, the decision block “Vdc >= V1” evaluated during the passive precharging in which the converter operates as a passive diode rectifier through the precharging resistor; see Section III.A: “A threshold voltage value of V1 is set for the dc-link voltage, in which the operation mode changes from the passive precharging to active precharging mode”), and enabling a voltage regulation to charge the AC to DC output to reach a reference voltage upon the detection (see Fig. 4 and Section III.A, the converter switching is enabled and “it linearly increases from V1 to its nominal reference value (V2)”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the operations of Pugliese to include detecting that the peak voltage of each of the DC bus has reached a first threshold voltage during the rectification stage and enabling the first voltage regulation upon the detection, as taught by Tafti, because it can limit the inrush current of the active front-end rectifier during the start-up process to its nominal current (see Abstract and Section III.A of Tafti).
The combination of Pugliese and Tafti does not disclose detecting that a PLL signal indicates a locked state with an AC grid voltage and enabling the first voltage regulation upon detecting the locked state (Tafti computes the grid voltage angle using a PLL, see Fig. 5 and Section III.B of Tafti, but does not explicitly disclose detecting the locked state as a condition for enabling the regulation).
However, Ahmed teaches (see Fig. 4) detecting whether a PLL signal indicates a locked state of synchronization with an AC grid voltage (see [0029] of Ahmed, the power converter operates in “a first phase locked loop (PLL) control mode 206 that establishes a state of synchronization with the electric grid 102”; see [0032] of Ahmed, “detecting a loss of the state of synchronization with the electric grid”), operating the converter in a diode rectification mode when the converter is not synchronized (see [0033] of Ahmed, “switching the converter to a diode mode of operation using a set of anti-parallel diodes, by blocking the converter pulses”), and enabling the closed-loop converter regulation upon detecting that the state of synchronization is established (see [0036] of Ahmed, “re-establishing the state of synchronization and initiating re-charge of the dc-link capacitors by restoring the normal converter control scheme”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the operations of Pugliese as modified in view of Tafti to include detecting that the PLL signal indicates the locked state with the AC grid voltage and enabling the first voltage regulation upon the detection, as taught by Ahmed, because it can prevent converter tripping caused by a synchronization error between the converter and the grid and allows the converter to resume normal regulated operation in a faster timeframe (see [0009] of Ahmed, “the converter resumes normal operation once synchronization is re-established, and normal operation of the grid is therefore re-enabled in a faster timeframe”).
The combination of Pugliese and Tafti does not disclose one or more computer-readable non-transitory storage media embodying software that is operable when executed to perform the operations.
However, Ahmed teaches (see Fig. 1) one or more computer-readable non-transitory storage media embodying software operable when executed to perform the converter control operations (see claim 13 of Ahmed: “A non-transitory computer readable memory storing instructions, the instructions executable in a processor”; see also [0017], [0019], and [0039] of Ahmed).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to embody the start-up control of Pugliese as modified in view of Tafti as software stored in one or more computer-readable non-transitory storage media, as taught by Ahmed, because it can implement the converter control functions as encoded software instructions executable in a processor.
Claims 2, 3, 6, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Pugliese in view of Tafti and Ahmed as applied to claims 1, 5, and 12 above, and further in view of Zhang (X. Zhang et al., “A Microprocessor Resource-Saving Dual Active Bridge Control for Startup and Restart of Three-Stage Modular Solid-State Transformer,” IEEE Transactions on Power Delivery, vol. 35, no. 3, pp. 1443-1454, June 2020).
Regarding claim 2, Pugliese discloses (see Fig. 16) generating control variables for the second voltage regulation based on the operation condition (see Section IV.B.2, the duty-cycle ramp is generated based on the input voltage, the maximum peak current, and the start-up time constraint; see Section IV.F, the ramp slope of each DAB converter is set based on the voltage difference of each cell), wherein the control variables comprise a first pulse width of a primary H-Bridge output voltage for each of the DAB converters (see Fig. 16 and Eq. (24) of Section IV.B.2, where (DTDAB)/2 denotes the time-shift representing the duration of the positive and negative voltage of the primary-side VP waveform, the primary-side switches being driven “varying the duty-cycle from zero to 1”) and a phase shift angle between the primary H-Bridge output voltage and the secondary H-Bridge output voltage (see Section IV.C: “Turning on the switches in the second DAB H-bridge and adjusting properly the value of φi (phase shift control variable), the control of Vo can be achieved”; see Section III, where φ is “the steady-state DAB phase shift angle between the voltages at the primary and secondary sides of the HFT”); and enabling the second voltage regulation of each of the plurality of DAB converters to reach the second reference voltage within the current limit based on the control variables (see Sections IV.B.2 and IV.C of Pugliese).
Pugliese does not disclose the control variables comprise a second pulse width of a secondary H-Bridge output voltage for each of the DAB converters.
However, Zhang teaches (see Fig. 5(a)) adjusting the pulse width of the primary H-bridge output voltage and the pulse width of the secondary H-bridge output voltage of a DAB converter (see p. 1445: “limits the inrush current by adding an inner phase shift θ to the full bridges of a DAB”; see p. 1446 and Fig. 5(a): “T1, T2 and T3, T4 also share no gate signals thus to achieve symmetry configuration thereby providing the possibility for start-up from the HV side”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include generating a second pulse width of the secondary H-Bridge output voltage for each of the DAB converters, as taught by Zhang, because it can provide the possibility of starting up from either side of the converter as well as supporting the voltage balancing process during restart operations (see p. 1446 of Zhang).
Regarding claim 3, as best understood, Pugliese does not disclose pre-charging the DC bus of the plurality of AC to DC converters with a power source connected to an output of the DAB converters, and enabling a reverse charging voltage regulation of each of the plurality of AC to DC converters being within the current limit based on the control variables.
However, Zhang teaches (see Fig. 1) pre-charging the DC bus of the plurality of AC to DC converters with a power source connected to an output of the DAB converters (see p. 1444, Section II.A: “Charge the LVDC bus by freewheeling diodes of the LV side DC/AC”, followed by charging the HV side cells by the DABs, wherein the LV grid is the power source connected at the parallel-connected DAB outputs), and enabling a reverse charging voltage regulation of each of the plurality of AC to DC converters being within the current limit based on the control variables (see p. 1444: “The LV side DC/AC boosts the LVDC voltage to the rated value and consequently increase the HV side cell voltages by DABs”; see pp. 1447-1448 and Eqs. (18)-(19) of Zhang, where the dead time Td is set so that the maximum DAB current Itmax does not exceed the current limit Itlimit).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include pre-charging the DC bus of the AC to DC converters with a power source connected to the output of the DAB converters and enabling the reverse charging voltage regulation within the current limit, as taught by Zhang, because it can enable the converter to start up when the grid feeds on the LV side of the converter (see p. 1444 of Zhang).
Regarding claim 6, Pugliese does not disclose monitoring an initial voltage value associated with the partial output voltage condition.
However, Zhang teaches (see Fig. 6) monitoring an initial voltage value associated with a partial output voltage condition (see p. 1447 of Zhang, where Up0 denotes the initial voltage of the HV cell capacitor voltage up at the beginning of the DAB charging step; see Eq. (26), p. 1449 of Zhang, where the varied dead time is obtained by monitoring the cell voltage up and the equivalent LVDC voltage us′; see pp. 1448-1450, the restart process starts from the measured initial cell voltages of 959 V and 891 V and the measured initial LVDC voltage of 742 V).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include monitoring an initial voltage value associated with the partial output voltage condition, as taught by Zhang, because it can maintain the magnitude of the DAB current within a normal range while reducing the overall time of the voltage balancing process (see p. 1447 and p. 1449 of Zhang).
Regarding claim 13, Pugliese discloses generating control variables for the second voltage regulation based on the operation condition (see Section IV.B.2, the duty-cycle ramp is generated based on the input voltage, the maximum peak current, and the start-up time constraint; see Section IV.F, the ramp slope of each DAB converter is set based on the voltage difference of each cell), wherein the control variables comprise a first pulse width of a primary H-Bridge output voltage for each of the DAB converters (see Fig. 16 and Eq. (24) of Section IV.B.2, where (DTDAB)/2 denotes the time-shift representing the duration of the positive and negative voltage of the primary-side VP waveform, the primary-side switches being driven “varying the duty-cycle from zero to 1”) and a phase shift angle between the primary H-Bridge output voltage and the secondary H-Bridge output voltage (see Section IV.C: “Turning on the switches in the second DAB H-bridge and adjusting properly the value of φi (phase shift control variable), the control of Vo can be achieved”; see Section III, where φ is “the steady-state DAB phase shift angle between the voltages at the primary and secondary sides of the HFT”); and enabling the second voltage regulation of each of the plurality of DAB converters to reach the second reference voltage within the current limit based on the control variables (see Sections IV.B.2 and IV.C of Pugliese).
Pugliese does not disclose the control variables comprise a second pulse width of a secondary H-Bridge output voltage for each of the DAB converters.
However, Zhang teaches (see Fig. 5(a)) adjusting the pulse width of the primary H-bridge output voltage and the pulse width of the secondary H-bridge output voltage of a DAB converter (see p. 1445: “limits the inrush current by adding an inner phase shift θ to the full bridges of a DAB”; see p. 1446 and Fig. 5(a): “T1, T2 and T3, T4 also share no gate signals thus to achieve symmetry configuration thereby providing the possibility for start-up from the HV side”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include generating a second pulse width of the secondary H-Bridge output voltage for each of the DAB converters, as taught by Zhang, because it can provide the possibility of starting up from either side of the converter as well as supporting the voltage balancing process during restart operations (see p. 1446 of Zhang).
Regarding claim 14, as best understood, Pugliese does not disclose pre-charging the DC bus of the plurality of AC to DC converters with a power source connected to an output of the DAB converters, and enabling a reverse charging voltage regulation of each of the plurality of AC to DC converters being within the current limit based on the control variables.
However, Zhang teaches (see Fig. 1) pre-charging the DC bus of the plurality of AC to DC converters with a power source connected to an output of the DAB converters (see p. 1444, Section II.A: “Charge the LVDC bus by freewheeling diodes of the LV side DC/AC”, followed by charging the HV side cells by the DABs, wherein the LV grid is the power source connected at the parallel-connected DAB outputs), and enabling a reverse charging voltage regulation of each of the plurality of AC to DC converters being within the current limit based on the control variables (see p. 1444: “The LV side DC/AC boosts the LVDC voltage to the rated value and consequently increase the HV side cell voltages by DABs”; see pp. 1447-1448 and Eqs. (18)-(19) of Zhang, where the dead time Td is set so that the maximum DAB current Itmax does not exceed the current limit Itlimit).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include pre-charging the DC bus of the AC to DC converters with a power source connected to the output of the DAB converters and enabling the reverse charging voltage regulation within the current limit, as taught by Zhang, because it can enable the converter to start up when the grid feeds on the LV side of the converter (see p. 1444 of Zhang).
Claims 7, 8, 9, 17, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pugliese in view of Tafti and Ahmed as applied to claims 1 and 12 above, and further in view of Liu (X. Liu et al., “A Start-Up Scheme for a Three-Stage Solid-State Transformer With Minimized Transformer Current Response,” IEEE Transactions on Power Electronics, vol. 27, no. 12, pp. 4832-4836, December 2012).
Regarding claim 7, Pugliese does not disclose wherein the monitored voltage condition of each of the plurality of AC to DC converters comprises the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage while the PLL signal indicates the locked state with the AC grid voltage.
However, Liu teaches (see Fig. 3) monitoring a first condition in which the AC to DC output has reached the first reference voltage (see p. 4834 and Fig. 3(a)-(b) of Liu, where after the diode-rectification stage ends “the relay will switch OFF the charging resistor and the closed-loop control of the rectifier is enabled” to regulate the capacitor voltage to the desired level; “the start-up of dc-dc converter is enabled after rectifier start-up finishes”) and a second condition in which the AC to DC output has reached the peak voltage at the end of the diode-rectification stage while the rectifier is synchronized to the grid by a PLL (see p. 4834 and Fig. 3(d): “the proposed scheme synchronizes the rectifier start-up and the dc-dc converter start-up in a controlled manner”, with both closed-loop controls beginning when the diode-rectification stage ends; see p. 4835 and Fig. 5, the rectifier control system includes a PLL).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include monitoring the condition in which the AC to DC output has reached the first reference voltage and the condition in which the AC to DC output has reached the peak voltage while the PLL signal indicates the locked state, as taught by Liu, because it can help coordinate the start-up of the DC-DC converter stage with the state of the rectifier stage to minimize the high-frequency transformer current and eliminate the input inrush current (see Abstract, p. 4832 of Liu).
Regarding claim 8, Pugliese does not disclose simultaneously enabling the second voltage regulation of each of the plurality of DAB converters to charge the DAB output to reach the second reference voltage when detecting the monitored voltage condition of each of the plurality of AC to DC converters has reached the first reference voltage.
However, Liu teaches (see Fig. 3(b)) enabling the voltage regulation of the DC-DC converter stage to charge its output to the reference voltage when the AC to DC output has reached the first reference voltage (see p. 4834 and Fig. 3(b): “the start-up of dc-dc converter is enabled after rectifier start-up finishes”, i.e., after the rectifier output voltage has reached the desired level). In the combination, the second voltage regulation of each of the plurality of DAB converters of Pugliese is enabled simultaneously, since the plurality of DAB converters of Pugliese are soft-started concurrently (see Section IV.F and Fig. 22 of Pugliese: “The maximum inrush current can be equally shared by the DAB converters changing properly the slope of the soft-shift start ramp of each converter”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include simultaneously enabling the second voltage regulation of each of the plurality of DAB converters when detecting the AC to DC outputs have reached the first reference voltage, as taught by Liu, because the input voltage of the DC-DC stage can be controlled to be constant by the rectifier stage, which can help provide a stable and regulated input voltage to the DAB converters during their start-up (see p. 4834 of Liu, where the input voltage Vin “is controlled to be constant by the rectifier stage after the rectifier start-up ends”).
Regarding claim 9, Pugliese does not disclose simultaneously enabling the second voltage regulation of each of the plurality of DAB converters to charge the DAB output to reach the second reference voltage when detecting the monitored voltage condition of each of the plurality of AC to DC converters has reached the peak voltage while the PLL signal indicates the locked state with the AC grid voltage.
However, Liu teaches (see Fig. 3(d)) enabling the voltage regulation of the DC-DC converter stage when the AC to DC output has reached the peak voltage at the end of the diode-rectification stage while the rectifier is synchronized to the grid by a PLL (see p. 4834 and Fig. 3(d): “the proposed scheme synchronizes the rectifier start-up and the dc-dc converter start-up in a controlled manner”; see p. 4835 and Fig. 5 of Liu, where the rectifier control system includes a PLL and the control reference for the dc-dc output is set to track the rectifier output “in order to realize the synchronized start-up with the rectifier”). (Examiner’s Note: In the combination, the second voltage regulation of each of the plurality of DAB converters of Pugliese is enabled simultaneously, since the plurality of DAB converters of Pugliese are soft-started concurrently (see Section IV.F and Fig. 22 of Pugliese: “The maximum inrush current can be equally shared by the DAB converters changing properly the slope of the soft-shift start ramp of each converter”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include simultaneously enabling the second voltage regulation of each of the plurality of DAB converters when detecting the AC to DC outputs have reached the peak voltage while the PLL signal indicates the locked state, as taught by Liu, because it can minimize the high-frequency transformer current during the start-up transient and eliminate the input inrush current at no extra cost (see p. 4834 of Liu).
Regarding claim 17, Pugliese does not disclose wherein the monitored voltage condition of each of the plurality of AC to DC converters comprises the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage while the PLL signal indicates the locked state with the AC grid voltage.
However, Liu teaches (see Fig. 3) monitoring a first condition in which the AC to DC output has reached the first reference voltage (see p. 4834 and Fig. 3(a)-(b) of Liu, where after the diode-rectification stage ends “the relay will switch OFF the charging resistor and the closed-loop control of the rectifier is enabled” to regulate the capacitor voltage to the desired level; “the start-up of dc-dc converter is enabled after rectifier start-up finishes”) and a second condition in which the AC to DC output has reached the peak voltage at the end of the diode-rectification stage while the rectifier is synchronized to the grid by a PLL (see p. 4834 and Fig. 3(d): “the proposed scheme synchronizes the rectifier start-up and the dc-dc converter start-up in a controlled manner”, with both closed-loop controls beginning when the diode-rectification stage ends; see p. 4835 and Fig. 5, the rectifier control system includes a PLL).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include monitoring the condition in which the AC to DC output has reached the first reference voltage and the condition in which the AC to DC output has reached the peak voltage while the PLL signal indicates the locked state, as taught by Liu, because it can coordinate the start-up of the DC-DC converter stage with the state of the rectifier stage to minimize the high-frequency transformer current and eliminate the input inrush current (see Abstract, p. 4832 of Liu).
Regarding claim 18, Pugliese does not disclose simultaneously enabling the second voltage regulation of each of the plurality of DAB converters to charge the DAB output to reach the second reference voltage when detecting the monitored voltage condition of each of the plurality of AC to DC converters has reached the first reference voltage.
However, Liu teaches (see Fig. 3(b)) enabling the voltage regulation of the DC-DC converter stage to charge its output to the reference voltage when the AC to DC output has reached the first reference voltage (see p. 4834 and Fig. 3(b): “the start-up of dc-dc converter is enabled after rectifier start-up finishes”, i.e., after the rectifier output voltage has reached the desired level). (Examiner’s Note: In the combination, the second voltage regulation of each of the plurality of DAB converters of Pugliese is enabled simultaneously, since the plurality of DAB converters of Pugliese are soft-started concurrently (see Section IV.F and Fig. 22 of Pugliese: “The maximum inrush current can be equally shared by the DAB converters changing properly the slope of the soft-shift start ramp of each converter”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include simultaneously enabling the second voltage regulation of each of the plurality of DAB converters when detecting the AC to DC outputs have reached the first reference voltage, as taught by Liu, because the input voltage of the DC-DC stage is then controlled to be constant by the rectifier stage, providing a stable and regulated input voltage to the DAB converters during their start-up (see p. 4834 of Liu).
Regarding claim 19, Pugliese does not disclose simultaneously enabling the second voltage regulation of each of the plurality of DAB converters to charge the DAB output to reach the second reference voltage when detecting the monitored voltage condition of each of the plurality of AC to DC converters has reached the peak voltage while the PLL signal indicates the locked state with the AC grid voltage.
However, Liu teaches (see Fig. 3(d)) enabling the voltage regulation of the DC-DC converter stage when the AC to DC output has reached the peak voltage at the end of the diode-rectification stage while the rectifier is synchronized to the grid by a PLL (see p. 4834 and Fig. 3(d): “the proposed scheme synchronizes the rectifier start-up and the dc-dc converter start-up in a controlled manner”; see p. 4835 and Fig. 5 of Liu, where the rectifier control system includes a PLL and the control reference for the dc-dc output is set to track the rectifier output “in order to realize the synchronized start-up with the rectifier”). (Examiner’s Note: In the combination, the second voltage regulation of each of the plurality of DAB converters of Pugliese is enabled simultaneously, since the plurality of DAB converters of Pugliese are soft-started concurrently (see Section IV.F and Fig. 22 of Pugliese: “The maximum inrush current can be equally shared by the DAB converters changing properly the slope of the soft-shift start ramp of each converter”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed to include simultaneously enabling the second voltage regulation of each of the plurality of DAB converters when detecting the AC to DC outputs have reached the peak voltage while the PLL signal indicates the locked state, as taught by Liu, because it can minimize the high-frequency transformer current during the start-up transient and eliminate the input inrush current at no extra cost (see p. 4834 of Liu).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Pugliese in view of Tafti and Ahmed as applied to claim 1 above, and further in view of Saeed (M. Saeed et al., “Energization and Start-Up of CHB-Based Modular Three-Stage Solid-State Transformers,” IEEE Transactions on Industry Applications, vol. 54, no. 5, pp. 5483-5492, 2018).
Regarding claim 11, Pugliese discloses (see Section IV.A) wherein the rectification stage for pre-charging DC bus of the plurality of AC to DC converters is enabled via a pre-charge system comprising a resistor for reducing an inrush current (see Section IV.A: “The system is charged through a precharging resistor connected between the grid and the ac side of the ac/dc converter in order to avoid a large inrush current”) that is subsequently bypassed (see Section IV.A: “The resistor is then by-passed meanwhile passive rectifier operation is perpetuated by the antiparallel freewheeling diodes of the CHB converter”).
Pugliese does not disclose the pre-charge switch system comprises a first switch and the resistor for reducing an inrush current, and a bypass second switch.
However, Tafti teaches (see Fig. 2) a pre-charge switch system comprising a first switch and the resistor for reducing an inrush current (see Section II of Tafti: “The circuit breaker CB1 is used for the connection/disconnection of the converter from the grid”, connected in series with the precharging resistor Rprecharge per Fig. 2), and a bypass second switch (see Section II of Tafti: “The circuit breaker CB2 bypasses the precharging resistor during the normal operation of the converter”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese to include the pre-charge switch system comprising a first switch and the resistor, and a bypass second switch, as taught by Tafti, because it can connect and disconnect the converter from the grid and bypass the pre-charging resistor during normal operation of the converter (see Section II and Fig. 2 of Tafti).
The combination of Pugliese as modified in view of Tafti and Ahmed does not disclose the bypass second switch operates when the peak voltage of each of the DC bus of plurality of AC to DC converters during the rectification stage has reached the first threshold voltage.
However, Saeed teaches (see Fig. 7) a bypass switch that operates when the peak voltage of each of the DC bus of the plurality of AC to DC converters during the rectification stage has reached the threshold voltage (see Section IV.A: “Pre-charging resistors are bypassed once the DC-links stabilize at the rectified voltage values”; see Fig. 7, step 5, where “Vcell and VdcLV match the corresponding grid rectified voltage. Pre-charge resistors are bypassed”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Pugliese as modified in view of Tafti and Ahmed such that the bypass second switch operates when the peak voltage of each of the DC bus has reached the first threshold voltage during the rectification stage, as taught by Saeed, because it can limit the inrush current flowing through the freewheeling diodes when the converter is connected to the grid while removing the pre-charge resistance from the power path once the DC-links have stabilized at the rectified voltage values (see Section IV.A of Saeed).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2022/0263405 A1 discloses a startup process for a dual active bridge converter with a DC bus pre-charge routine and current limiting.
US 2022/0399819 A1 discloses dual active bridge converter control with an intra-bridge phase shift computed based on the sensed output voltage.
US 2021/0336550 A1 discloses a method for pre-charging a cascade converter using uncontrolled rectification and threshold-triggered closed-loop PWM control.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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