DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 9, 11-12, 15, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over BiRen (CN 118138440 A, hereinafter “BiRen”) in view of Dai (CN 113448810 A, hereinafter “Dai”). A machine-translated English version for BiRen and Dai is attached, respectively.
Regarding claim 1, BiRen discloses A system comprising:
multiple accelerator units positioned in a physical configuration; and (page 2, lines 1-3, “In AI server systems, there is usually more than one GPU (graphics processing unit) card. Currently, common AI (Artificial Intelligence) servers are 2U4 cards, 4U8 cards, and 8U8 cards”). Note that: (1) a GPU card or baseboard with 2U4, 4U8, or 8U8 layout is a physical configuration for multiple GPUs as multiple accelerator units and the corresponding GPUs are mounted or positioned on the GPU card; and (2) an AI server is a system.
However, BiRen fails to disclose, but in the same art of accelerator based computing system, Dai discloses
indexer circuitry configured to enumerate each accelerator unit of the multiple accelerator units with an index number that indicates a physical location of the accelerator unit within the physical configuration. (Dai, page 2, lines 12-18, “monitoring and alarming of GPU PCIE link states are mainly completed by interaction between a BIOS and a BMC, a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU and cannot change along with the change of the number of the GPUs, the serial number of the GPU under a system, the serial number of the GPU in BMC asset information and the serial number of the GPU on a board card are consistent in silk-screen printing”). Note that: (1) the BIOS and BMC (baseboard manager controller) can be combined to form an indexer circuitry that enumerates the GPUs on the baseboard according to an enumeration sequence of the 8 GPUs; (2) a BIOS has a respective number bound with a physical position location of the GPU of the multiple GPSs (8 GPUs) as an ID for each GPU, and the number can be regarded as an index of each GPU position on a baseboard or a card according to an enumeration sequence of the 8 GPUs; (3) since the serial numbers of each GPU are consistent in a system, MBC assent information and the board silk printing (marking), the physical location of each GPU is identified; (4) it is obvious to one having skill in the art that the index of each GPU position on a baseboard or a card can be combined with the baseboard or card ID represent by the BMC to form an expanded index for a GPU physical location to be indicated at both system, card, and other levels (e.g., racks).
BiRen and Dai are in the same field of endeavor, namely accelerator based computing system. Before the effective filing date of the claimed invention, it would have been obvious to apply creating and enumerating each accelerator (GPU) according to an enumeration sequence with an index number indicating its physical location, as taught by Dai into BiRen. The motivation would have been “a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU” (Dai, page 2, lines 13-15). The suggestion for doing so would allow to have an indexer circuitry to enumerate each accelerator (GPU) according to an enumeration sequence with an index number indicating its physical location. Therefore, it would have been obvious to combine BiRen and Dai.
Regarding claim 2, BiRen in view of Dai discloses The system of claim 1, wherein the accelerator unit comprises a graphics processing unit (GPU), neural network engine (NNE), neural processing unit (NPU), inference processing unit (IPU), accelerated processing unit (APU), vision processing unit (VPU), digital signal processor (DSP), or field-programmable gate array (FPGA). (Dai, page 2, line 4, “computing mode formed by combining processors such as CPU, GPU, FPGA, ASIC, etc.”). Note that: the accelerator unit can be GPU, FPGA, or ASIC.
The motivation to combine BiRen and Dai given in claim 1 is incorporated here.
Regarding claim 6, BiRen in view of Dai discloses The system of claim 1, wherein the system comprises a server of multiple servers within a data center. (BiRen, page 1, Abstract, “In AI server systems, there is usually more than one GPU (graphics processing unit) card. Currently, common AI (Artificial Intelligence) servers are 2U4 cards, 4U8 cards, and 8U8 cards. In addition, dozens or even hundreds of AI servers are often deployed in a data center.”). Note that: the system can include an AI server of dozens or even hundreds of AI servers deployed in a data center.
Regarding claim 9, BiRen in view of Dai discloses The system of claim 1, wherein the indexer circuitry includes software or firmware in a basic input/output system (BIOS) of the multiple accelerator units, an operating system of the system, or a hypervisor of the system. (Dai, page 2, lines 12-18, “monitoring and alarming of GPU PCIE link states are mainly completed by interaction between a BIOS and a BMC, a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU and cannot change along with the change of the number of the GPUs, the serial number of the GPU under a system, the serial number of the GPU in BMC asset information and the serial number of the GPU on a board card are consistent in silk-screen printing”). Note that: the indexer circuitry includes BIOS firmware.
The motivation to combine BiRen and Dai given in claim 1 is incorporated here.
Regarding claim 11, BiRen in view of Dai discloses A method comprising: (BiRen, page 1, lines 1-2, “Positioning method of physical position of GPU card in 1 server cluster and server”).
outputting the index identifier of a first accelerator unit of the multiple accelerator units to be serviced. (BiRen, page 8, line 15-18, “displaying GPU information and Link states transmitted by the BIOS in an asset information 15 list under a BMC management webpage; if the GPU has the speed reduction or Lane 16 reduction situation, corresponding log recording and lightening of a warning lamp are 17 carried out”). Note that: the index identifier can be included in the GPU information be output or displayed under a BMC management webpage.
enumerating, by indexer circuitry, each accelerator unit of multiple accelerator units in a computing device with an index identifier indicating a physical location of each accelerator unit within the computing device; and (Dai, page 2, lines 12-18, “monitoring and alarming of GPU PCIE link states are mainly completed by interaction between a BIOS and a BMC, a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU and cannot change along with the change of the number of the GPUs, the serial number of the GPU under a system, the serial number of the GPU in BMC asset information and the serial number of the GPU on a board card are consistent in silk-screen printing”). Note that: (1) the BIOS and BMC (baseboard manager controller) can be combined to form an indexer circuitry that enumerates the GPUs on the baseboard according to an enumeration sequence of the 8 GPUs; (2) a BIOS has a respective number bound with a physical position location of the GPU of the multiple GPSs (8 GPUs) as an ID for each GPU, and the number can be regarded as an index of each GPU position on a baseboard or a card according to an enumeration sequence of the 8 GPUs; (3) since the serial numbers of each GPU are consistent in a system, MBC assent information and the board silk printing (marking), the physical location of each GPU is identified; (4) it is obvious to one having skill in the art that the index of each GPU position on a baseboard or a card can be combined with the baseboard or card ID represent by the BMC to form an expanded index for a GPU physical location to be indicated at both system, card, and other levels (e.g., racks).
The motivation to combine BiRen and Dai given in claim 1 is incorporated here.
Regarding claim 12, BiRen in view of Dai discloses The method of claim 11, wherein the computing device comprises a server. (BiRen, page 1, Abstract, “In AI server systems, there is usually more than one GPU (graphics processing unit) card. Currently, common AI (Artificial Intelligence) servers are 2U4 cards, 4U8 cards, and 8U8 cards. In addition, dozens or even hundreds of AI servers are often deployed in a data center.”). Note that: the computing device can include an AI server of dozens or even hundreds of AI servers deployed in a data center.
Claim 15 is corresponding to claim 9. Therefore, claim 15 is rejected for the same rationale for claim 9.
Regarding claim 17, BiRen in view of Dai discloses An accelerator unit comprising: (BiRen, page 2, lines 1-3, “In AI server systems, there is usually more than one GPU (graphics processing unit) card. Currently, common AI (Artificial Intelligence) servers are 2U4 cards, 4U8 cards, and 8U8 cards”). Note that: a GPU card or baseboard with 2U4, 4U8, or 8U8 layout is a physical configuration for multiple GPUs as multiple accelerator units and the corresponding GPUs are mounted or positioned on the GPU card.
indexer circuitry configured to enumerate the accelerator unit with an index identifier that indicates a physical location of the accelerator unit within a physical configuration of multiple accelerator units on a baseboard. (Dai, page 2, lines 12-18, “monitoring and alarming of GPU PCIE link states are mainly completed by interaction between a BIOS and a BMC, a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU and cannot change along with the change of the number of the GPUs, the serial number of the GPU under a system, the serial number of the GPU in BMC asset information and the serial number of the GPU on a board card are consistent in silk-screen printing”). Note that: (1) the BIOS and BMC (baseboard manager controller) can be combined to form an indexer circuitry that enumerates the GPUs on the baseboard according to an enumeration sequence of the 8 GPUs; (2) a BIOS has a respective number bound with a physical position location of the GPU of the multiple GPSs (8 GPUs) as an ID for each GPU, and the number can be regarded as an index of each GPU position on a baseboard or a card according to an enumeration sequence of the 8 GPUs; (3) since the serial numbers of each GPU are consistent in a system, MBC assent information and the board silk printing (marking), the physical location of each GPU is identified; (4) it is obvious to one having skill in the art that the index of each GPU position on a baseboard or a card can be combined with the baseboard or card ID represent by the BMC to form an expanded index for a GPU physical location to be indicated at both system, card, and other levels (e.g., racks).
The motivation to combine BiRen and Dai given in claim 1 is incorporated here.
Claim 19 is corresponding to claim 2. Therefore, claim 19 is rejected for the same rationale for claim 2.
Claims 3-5, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of BiRen, Dai, Open Compute Project (OCPREG19 - OAI-UBB Universal baseboard for OCP Accelerator Module, YouTube.com, link: https://youtu.be/2cegD14MtNs?si=sHGGshLSNYHncq1, hereinafter, “Open_Compute_Project”), and Wiki_grid (Regular grid, archive.org, https://web.archive.org/web/20240812222138/https://en.wikipedia.org/wiki/Regular_grid, hereinafter “Wiki_grid”).
Regarding claim 3, BiRen in view of Dai discloses The system of claim 1, wherein:
However, BiRen in view of Dai fails to discloses, but in the same art of accelerator based computing system, Open_Compute_Project discloses
the physical configuration is a two-dimensional (2D) rectangle; and (Open_Compute_Project, page 1, lines 8-9, “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration”).
BiRen in view of Dai, and Open_Compute_Project, are in the same field of endeavor, namely accelerator based computing system. Before the effective filing date of the claimed invention, it would have been obvious to apply a physical configuration being a two-dimensional (2D) rectangle, as taught by Open_Compute_Project into BiRen in view of Dai. The motivation would have been “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration” (Open_Compute_Project, page 1, lines 8-9). The suggestion for doing so would allow to have a 2D rectangle as the physical configuration. Therefore, it would have been obvious to combine BiRen, Dai, and Open_Compute_Project.
However, the combination of BiRen, Dai, and Open_Compute_Project fails to disclose, but in the same art of computing application, Wiki_grid discloses
the index number indicates a horizontal position and a vertical position of the accelerator unit within the 2D rectangle. (Wiki_grid, page 1, para. 3, “Each cell in the grid can be addressed by index (i, j) in two dimensions”; page 1, para. 5, “A rectilinear grid is a tessellation by rectangles or rectangular cuboids (also known as rectangular parallelepipeds) that are not, in general, all congruent to each other”). Note that: the cell to represent an accelerate unit (OAM above) in the 2D rectangle can be indicated by index number (i, j) while i and j indicate a horizontal position and a vertical position of the accelerator unit, respectively.
The combination of BiRen, Dai, and Open_Compute_Project, and Wiki_grid, are in the same field of endeavor, namely accelerator based computing application. Before the effective filing date of the claimed invention, it would have been obvious to apply obtaining index number to indicate cell position (e.g., (i, j), (i,j,k), or angular) for rectilinear grids and curvilinear grids, as taught by Wiki_grid into the combination of BiRen, Dai, and Open_Compute_Project. The motivation would have been “Each cell in the grid can be addressed by index (i, j) in dimensions or (i, j, k) in three dimensions” (Wiki_grid, page 1, para. 3), and “
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” 2D curvilinear or circular grid (Wiki_grid, page 2). The suggestion for doing so would allow to have index for a 2D rectangle, a 3D cuboid, or a 2D circle as the physical configuration. Therefore, it would have been obvious to combine BiRen, Dai, Open_Compute_Project, and Wiki_grid.
Regarding claim 4, BiRen in view Dai discloses The system of claim 1, wherein:
However, BiRen in view of Dai fails to discloses, but in the same art of accelerator based computing system, Open_Compute_Project discloses
the physical configuration is a three-dimensional (3D) cuboid; (Open_Compute_Project, page 1, lines 10-12, “Video clip 30:28-31:55: Reference UBBs can have 22 layers with the “PCB Stack-up”; each PCB thickness: 128mil; by PCB stacking-up, the physical configuration of an UBB can be a 3D cuboid with an additional axis in stack-up direction”).
BiRen in view of Dai, and Open_Compute_Project, are in the same field of endeavor, namely accelerator based computing system. Before the effective filing date of the claimed invention, it would have been obvious to apply a physical configuration being a three-dimensional (3D) cuboid, as taught by Open_Compute_Project into BiRen in view of Dai. The motivation would have been “Video clip 30:28-31:55: Reference UBBs can have 22 layers with the “PCB Stack-up”; each PCB thickness: 128mil; by PCB stacking-up, the physical configuration of an UBB can be a 3D cuboid with an additional axis in stack-up direction” (Open_Compute_Project, page 1, lines 11-12). The suggestion for doing so would allow to have a 3D cuboid as the physical configuration. Therefore, it would have been obvious to combine BiRen, Dai, and Open_Compute_Project.
However, the combination of BiRen, Dai, and Open_Compute_Project fails to disclose, but in the same art of computing application, Wiki_grid discloses
and the index number indicates a horizontal position, a vertical position, and a depth position of the accelerator unit within the 3D cuboid. (Wiki_grid, page 1, para. 3, “Each cell in the grid can be addressed by index … (i, j, k) in three dimensions”; page 1, para. 5, “A rectilinear grid is a tessellation by rectangles or rectangular cuboids (also known as rectangular parallelepipeds) that are not, in general, all congruent to each other”). Note that: the cell to represent an accelerate unit (OAM above) in the 3D Cuboid can be indicated by index number (i, j, k) while i, j, and k indicate a horizontal position, a vertical position, and a depth and of the accelerator unit, respectively.
The motivation to combine BiRen, Dai, Open_Compute_Project, and Wiki_grid given for claim 3 is incorporated here.
Regarding claim 5, the combination of BiRen, Dai, and Open_Compute_Project discloses The system of claim 1, wherein:
the physical configuration is a two-dimensional (2D) rectangle (Open_Compute_Project, page 1, lines 8-9, “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration”).
The motivation to combine BiRen, Dai, and Open_Compute_Project given in 3 is incorporated here.
However, the combination of BiRen, Dai, and Open_Compute_Project fails to disclose, but in the same art of computing application, Wiki_grid discloses
Circle (Wiki_grid, page 2, “
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”). Note that: (1) while Wiki_grid only shows a quarter part of a set of circles, it is obvious to one having ordinary skill in the art that a whole 2D circle can be obtained by expanding the quart circle by mirroring it in horizontal and vertical directions; and (2) a 2D circle can substitute a 2D rectangle as the physical configuration for accelerator units.
the index number indicates an angular position of the accelerator unit within the 2D circle. (Wiki_grid, page 2, “
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”; page 1, “A curvilinear grid or structured grid is a grid with the same combinatorial structure as a regular grid, in which the cells are quadrilaterals or [general] cuboids, rather than rectangles or rectangular cuboids”). Note that: for the “2-D curvilinear grid” shown above, it is obvious to one having ordinary skill in the art that the cell to represent an accelerate unit (OAM above) within the 2D circle can be indicated by an index number i degree of a range of 0-360 degree.
The motivation to combine BiRen, Dai, Open_Compute_Project, and Wiki_grid given for claim 3 is incorporated here.
Regarding claim 13, the combination of BiRen, Dai, Open_Compute_Project, and Wiki_grid discloses The method of claim 11, wherein
a physical configuration of the multiple accelerator units in the computing device. (Open_Compute_Project, page 1, lines 8-9, “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration”).
the index identifier is provided in a coordinate system corresponding to a physical configuration of the multiple accelerator units in the computing device. (Wiki_grid, page 1, para. 3, “Each cell in the grid can be addressed by index (i, j) in two dimensions”; page 1, para. 5, “A rectilinear grid is a tessellation by rectangles or rectangular cuboids (also known as rectangular parallelepipeds) that are not, in general, all congruent to each other”). Note that: the cell to represent an accelerate unit (OAM above) in the 2D rectangle can be indicated by index number (i, j) while i and j indicate a horizontal position and a vertical position of the accelerator unit while the horizontal and vertical direction form a coordinate system, respectively.
The motivation to combine BiRen, Dai, Open_Compute_Project, and Wiki_grid given in claim 3 is incorporated here.
Claim 20 is corresponding to claim 13. Therefore, claim 20 is rejected for the same rationale for claim 13.
Claims 7-8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over BiRen in view of Dai and Open_Compute_Project.
Regarding claim 7, the combination of BiRen in view of Dai discloses The system of claim 1, wherein
However, BiRen in view of Dai fails to discloses, but in the same art of accelerator based computing system, Open_Compute_Project discloses
the multiple accelerator units are mounted on a universal baseboard according to an Open Compute Project (OCP) Accelerator Module (OAM) specification. (Open_Compute_Project, page 1, lines 8-9, “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration”). Note that: (1) 8 OAMs are mounted on a universal baseboard (UBB) according to an Open Compute Project (OCP) Accelerator Module (OAM) specification; and (2) the video clip is made by OCP according to an Open Compute Project (OCP) Accelerator Module (OAM) specification.
BiRen in view of Dai, and Open_Compute_Project, are in the same field of endeavor, namely accelerator based computing system. Before the effective filing date of the claimed invention, it would have been obvious to apply mounting multiple accelerator units on a UBB according to an Open Compute Project (OCP) Accelerator Module (OAM) specification, as taught by Open_Compute_Project into BiRen in view of Dai. The motivation would have been “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration” (Open_Compute_Project, page 1, lines 8-9). The suggestion for doing so would allow to mount multiple accelerator units on a UBB according to an Open Compute Project (OCP) Accelerator Module (OAM) specification. Therefore, it would have been obvious to combine BiRen, Dai, and Open_Compute_Project.
Regarding claim 8, the combination of BiRen, Dai, and Open_Compute_Project discloses The system of claim 7, wherein the universal baseboard includes markings corresponding to the index number of each accelerator unit. (Dai, page 2, lines 13-18, “a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU and cannot change along with the change of the number of the GPUs, the serial number of the GPU under a system, the serial number of the GPU in BMC asset information and the serial number of the GPU on a board card are consistent in silk-screen printing”). Note that: since the silk printing is a kind of markings and the index of each GPU is consistent with the silk printing, the silk printing on a card or board (UBB) with the multiple accelerator units mounted, is corresponding to the index number of each accelerator unit.
Regarding claim 14, BiRen in view of Dai and Open Compute Project discloses The method of claim 11, wherein the multiple accelerator units are mounted on a baseboard or chassis according to a known specification. (Open_Compute_Project, page 1, lines 8-9, “Video clip 6:16-6:50: 8* OAMs in UBB, UBB with OAMs including 8 OAMs using a 4-row / 2 column layout as a 2D rectangle for the physical configuration”). Note that: (1) 8 OAMs are mounted on a universal baseboard (UBB) according to an Open Compute Project (OCP) Accelerator Module (OAM) specification; and (2) the video clip is made by OCP according to an Open Compute Project (OCP) Accelerator Module (OAM) specification as a known specification.
The motivation to combine BiRen, Dai, and Open_Compute_Project given in claim 7 is incorporated here.
Claims 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of BiRen, Dai, and Wiki_grid.
Regarding claim 10, BiRen in view of Dai discloses The system of claim 1, wherein
However, BiRen in view of Dai fails to disclose, but in the same art of computing application, Wiki_grid discloses
the index number is provided as a value in base-two, base-ten, or base-16 format. (Wiki_grid, page 1, para. 3, “Each cell in the grid can be addressed by index (i, j) in two dimensions or (i, j, k) in three dimensions”). Note that: i, j, k for the index of the cell (accelerator unit) are conventionally taken as a base-10 integer, respectively.
BiRen in view of Dai, and Wiki_grid, are in the same field of endeavor, namely computing application. Before the effective filing date of the claimed invention, it would have been obvious to apply a value in 10-base format for index number, as taught by Wiki_grid into BiRen in view of Dai. The motivation would have been “Each cell in the grid can be addressed by index (i, j) in two dimensions or (i, j, k) in three dimensions” (Open_Compute_Project, page 1, para. 3). The suggestion for doing so would allow to have index number in 10-base format. Therefore, it would have been obvious to combine BiRen, Dai, and Wiki_grid.
Claim 16 is corresponding to claim 10. Therefore, claim 16 is rejected for the same rationale for claim 10.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of BiRen, Dai, and Wiki_VBIOS (Video BIOS, archive.org, https://web.archive.org/web/20240824112332/https://en.wikipedia.org/wiki/Video_BIOS, hereinafter “Wiki_VBIOS”).
Regarding claim 18, BiRen in view of Dai discloses The accelerator unit of claim 17, wherein the indexer circuitry includes (Dai, page 2, lines 12-18, “monitoring and alarming of GPU PCIE link states are mainly completed by interaction between a BIOS and a BMC, a BIOS firmware in a PCH has a number for asset information management for 8 GPUs according to an enumeration sequence of the 8 GPUs PCIE, the number is bound with a physical position of the GPU and cannot change along with the change of the number of the GPUs, the serial number of the GPU under a system, the serial number of the GPU in BMC asset information and the serial number of the GPU on a board card are consistent in silk-screen printing”). Note that: the indexer circuitry includes BIOS firmware.
However, BiRen in view of Dai fails to discloses, but in the same art of accelerator based computing system, Wiki_VBIOS discloses a video basic input / output system (VBIOS) (Wiki_VBIOS, page 1, paras. 1-2, “Video BIOS is the BIOS of a graphics card in a (usually IBM PCderived) computer. It initializes the graphics card at the computer's boot time. It also implements INT 10h interrupt and VESA BIOS Extensions (VBEi11 [2] for basic text and videomode output before a specific video driver is loaded … the video BIOS provides a set of video-related functions that are used by programs to access the video hardware as well as storing vendor-specific settings such as card name, clock frequencies, VRAM types & voltages. The video BIOS interfaces software to the video chipset in the same way that the system BIOS does for the system chipset.”). Note that: (1) VBIOS can substitute BIOS for the video card with video processing accelerator units (e.g., GPUs) mounted; and (2) it is known that VBIOS provides functions for video processing accelerator units (e.g., physical positioning for accelerator unit(s) as a part of the indexer circuitry) like BIOS for other accelerator units.
BiRen in view of Dai, and Wiki_VBIOS, are in the same field of endeavor, namely computing application. Before the effective filing date of the claimed invention, it would have been obvious to apply a VBIOS, as taught by Wiki_VBIOS into BiRen in view of Dai. The motivation would have been “the video BIOS provides a set of video-related functions that are used by programs to access the video hardware as well as storing vendor-specific settings such as card name, clock frequencies, VRAM types & voltages. The video BIOS interfaces software to the video chipset in the same way that the system BIOS does for the system chipset.” (Wiki_VBIOS, page 1, para. 2). The suggestion for doing so would allow to substitute a BIOS with a VBIOS to provides functions for video processing accelerator units (e.g., physical positioning for accelerator unit(s) as a part of the indexer circuitry) like BIOS for other accelerator units. Therefore, it would have been obvious to combine BiRen, Dai, and Wiki_VBIOS.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhao (Sharing a common form factor for accelerator modules, archive.org, https://web.archive.org/web/20240828175934/https://engineering.fb.com/2019/03/14/data-center-engineering/accelerator-modules/) teaches “To keep up with those demands, our industry is producing new types of accelerators for machine learning, deep learning, and high-performance computing for various types of hardware - GPUs, FPGAs, ASICs, IPU, NPUs, xPUs, and the list goes on”.
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/Biao Chen/
Patent Examiner, Art Unit 2611
/KEE M TUNG/Supervisory Patent Examiner, Art Unit 2611
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