DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Amendments filed on 05/27/2026 has been entered. Claim 1 has been amended and claims 11-12 have been canceled.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claims 1-2, 5, 9, 13-14, 17 and 35-36 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 7, 11 14-15, and 33-34 of U.S. Pub 18/984,756. Although the claims at issue are not identical, they are not patentably distinct from each other because.
18/984,733 (claim 1)
18/984,756 (claim 1)
A display panel, comprising: a display region;
A display panel, comprising: a display region;
at least two functional component regions, wherein the display region at least partially surrounds the at least two functional component regions, and the at least two functional component regions are arranged along a first direction and comprise a first functional component region and a second functional component region; and
at least two functional component regions, wherein the display region at least partially surrounds the at least two functional component regions, the at least two functional component regions comprise a first functional component region and a second functional component region that are arranged along a first direction;
first signal lines located in the display region, wherein at least part of each first signal line of the first signal lines extends in a first direction, and the first signal lines are arranged in a second direction intersecting with the first direction, wherein the first signal lines comprise at least one first-type signal line and at least one second-type signal line,
first signal lines located in the display region, wherein at least part of each first signal line of the first signal lines extends in a first direction, and the first signal lines are arranged in a second direction intersecting with the first direction, wherein the first signal lines comprise at least one first-type signal line and at least one second-type signal line,
wherein the at least one first-type signal line comprises at least two first-type connecting line, and one of the at least two first-type connecting line electrically connects parts of one of the at least one first-type signal line that are located at two sides of the first functional component region, another one of the at least two first-type connecting line electrically connects parts of one of the at least one first-type signal line that are located at two sides of the second functional component region, and
wherein one of the at least one first-type signal line at least partially surrounds the at least two functional component regions,
the at least one second-type signal line comprises a second-type connecting line, and the second-type connecting line electrically connects parts of one of the at least one second-type signal line that are located at two sides of one of the at least two functional component regions, and the at least one second-type signal line is broken at two sides of the another one of the at least two functional component regions;
the at least one second-type signal line comprises a control signal line, and the at least one second-type signal line is broken at two sides of one functional component region of the at least two functional component regions in the first direction;
wherein the at least one second-type signal line comprises a control signal line,
the at least one second-type signal line comprises a control signal line,
the display panel further has a second non-display region that at least partially surrounds the display region
a second non-display region at least partially surrounding the display region;
a first-type driving circuit located in the second non-display region and electrically connected to one of the at least one first-type signal line and located at a side of the display region in the first direction, and
a first-type driving circuit located in the second non-display region and electrically connected to one of the at least one first-type signal line and located at a side of the display region in the first direction;
second-type driving circuits located in the second non-display region and electrically connected to the control signal line and located at two sides of the display region in the first direction;
second-type driving circuits located in the second non-display region and electrically connected to the control signal line and located at two sides of the display region in the first direction,
wherein the at least one first-type signal line comprises at least one first-type connecting line, wherein one of the at least one first-type connecting line electrically connects parts of one first-type signal line of the at least one first-type signal line that are located at two sides of one of the at least one functional component region;
wherein the at least one first-type signal line comprises at least one first-type connecting line, wherein one of the at least one first-type connecting line electrically connects parts of one first-type signal line of the at least one first-type signal line that are located at two sides of one of the at least one functional component region,
wherein the display panel further comprises pixel driving circuit groups arranged in the display region along the second direction, wherein each pixel driving circuit group of the pixel driving circuit groups comprises at least two pixel driving circuit rows arranged in the second direction, wherein each pixel driving circuit row of the at least two pixel driving circuit rows comprises pixel driving circuits arranged in the first direction;
wherein the display panel further comprises pixel driving circuit groups arranged in the display region along the second direction, wherein each pixel driving circuit group of the pixel driving circuit groups comprises at least two pixel driving circuit rows arranged in the second direction, wherein each pixel driving circuit row of the at least two pixel driving circuit rows comprises pixel driving circuits arranged in the first direction
wherein the at least one first-type signal line comprises a plurality of first-type signal lines, the first-type driving circuit comprises first-type driving units that are cascaded, wherein one of the first-type driving units is electrically connected to the at least two pixel driving circuit rows in one pixel driving circuit group of the pixel driving circuit groups through at least two first-type signal lines of the plurality of first-type signal lines; and
wherein the at least one first-type signal line comprises a plurality of first-type signal lines, the first-type driving circuit comprises first-type driving units that are cascaded, wherein one of the first-type driving units is electrically connected to the at least two pixel driving circuit rows in one pixel driving circuit group of the pixel driving circuit groups through at least two first-type signal lines of the plurality of first-type signal lines, and
wherein the display panel further comprises at least one first jointing line, wherein at least two of the plurality of first-type signal lines that are electrically connected to the at least two pixel driving circuit rows in one pixel driving circuit group of the pixel driving circuit groups are electrically connected to one of the at least one first jointing line, and the one of the at least one first jointing line is electrically connected to the at least one first-type connecting line.
wherein the display panel further comprises at least one first jointing line, wherein at least two of the plurality of first-type signal lines that are electrically connected to the at least two pixel driving circuit rows in one pixel driving circuit group of the pixel driving circuit groups are electrically connected to one of the at least one first jointing line, and the one of the at least one first jointing line is electrically connected to the at least one first-type connecting line.
18/984,733 (claim 2)
18/984,756 (claim 2)
The display panel according to claim 1, wherein the display panel further comprises a dummy line extending in the second direction and comprises a first edge and a second edge that are opposite to each other in the first direction, wherein a distance dl between the first edge and the dummy line and a distance d2 between the second edge and the dummy line satisfy 0.9<dl/d2<1.1, and wherein the dummy line passes through the first functional component region, and one of the at least one second-type signal line is broken at two sides of the first functional component region in the first direction.
The display panel according to claim 1, wherein the display panel further comprises a dummy line extending in the second direction and comprises a first edge and second edge that are opposite to each other in the first direction, wherein a distance dl between the first edge and the dummy line and a distance d2 between the second edge and the dummy line satisfy 0.9<dl/d2<1.1, and wherein the dummy line passes through the first functional component region, and one of the at least one second-type signal line is broken at two sides of the first functional component region in the first direction.
18/984,733 (claim 5)
18/984,756 (claims 1 and 7)
The display panel according to claim 1, wherein the display panel further has a first non-display region located between the display region and one of the at least two functional component regions, wherein at least part of one first connecting line of the at least one first connecting line is located in the first non-display region.
a first non-display region located between the display region and one of the at least two functional component regions; The display panel according to claim 5, wherein at least part of one first connecting line of the at least one first connecting line is located in the first non-display region.
18/984,733 (claim 9)
18/984,756 (claims 11)
The display panel according to claim 1, wherein the first signal lines comprise at least two first signal lines corresponding to the at least two functional component regions, wherein in the second direction, at least two first connecting lines in the at least two first signal lines are located at a same side of the at least two functional component regions.
The display panel according to claim 5, wherein the first signal lines comprise at least two first signal lines corresponding to the at least two functional component regions, wherein in the second direction, at least two first connecting lines in the at least two first signal lines are located at a same side of the at least two functional component regions.
18/984,733 (claim 13)
18/984,756 (claims 14)
The display panel according to claim 12, further comprising: pixel driving circuits located in the display region, wherein each of the pixel driving circuit comprises: a driving transistor, a light-emitting control circuit having a control terminal electrically connected to a light-emitting control signal line, a gate reset circuit having a control terminal electrically connected to a first scanning control signal line and an input terminal electrically connected to a first reset signal line, a data input circuit having a control terminal electrically connected to one second scanning control signal line of second scanning control signal lines, a threshold voltage compensation circuit having a control terminal electrically connected to a third scanning control signal line, a bias adjusting circuit having a control terminal electrically connected to a fourth scanning control signal line and a signal adjusting line, and a light-emitting element reset circuit having an input terminal electrically connected to a second reset signal line, wherein the at least one first-type signal line comprises at least one of the light-emitting control signal line, the first scanning control signal line, the third scanning control signal line, or the fourth scanning control signal line; and the control signal line comprises the one second scanning control signal line.
The display panel according to claim 1, further comprising: pixel driving circuits located in the display region, wherein each of the pixel driving circuit comprises: a driving transistor, a light-emitting control circuit having a control terminal electrically connected to a light-emitting control signal line, a gate reset circuit having a control terminal electrically connected to a first scanning control signal line and an input terminal electrically connected to a first reset signal line, a data input circuit having a control terminal electrically connected to one second scanning control signal line of second scanning control signal lines, a threshold voltage compensation circuit having a control terminal electrically connected to a third scanning control signal line, a bias adjusting circuit having a control terminal electrically connected to a fourth scanning control signal line, and a light-emitting element reset circuit having an input terminal electrically connected to a second reset signal line, wherein the at least one first-type signal line comprises at least one of the light-emitting control signal line, the first scanning control signal line, the third scanning control signal line, or the fourth scanning control signal line; and the control signal line comprises the one second scanning control signal line.
18/984,733 (claim 14)
18/984,756 (claims 15)
The display panel according to claim 1, wherein the display region comprises pixel driving circuits; and the at least one second-type signal line comprises a functional signal line, wherein the functional signal line is configured to transmit a constant signal and is electrically connected to an input terminal of the pixel driving circuit.
The display panel according to claim 14, wherein the at least one second- type signal line further comprises a functional signal line, wherein the functional signal line is configured to transmit a constant signal and is electrically connected to an input terminal of the pixel driving circuit.
18/984,733 (claim 17)
18/984,756 (claims 14)
The display panel according to claim 14, wherein at least one of the pixel driving circuits comprises a light-emitting element reset circuit, an input terminal of the light- emitting element reset circuit is electrically connected to a second reset signal line, and the functional signal line comprises the second reset signal line.
The display panel according to claim 1, further comprising: pixel driving circuits located in the display region, wherein each of the pixel driving circuit comprises: a driving transistor, a light-emitting control circuit having a control terminal electrically connected to a light-emitting control signal line, a gate reset circuit having a control terminal electrically connected to a first scanning control signal line and an input terminal electrically connected to a first reset signal line, a data input circuit having a control terminal electrically connected to one second scanning control signal line of second scanning control signal lines, a threshold voltage compensation circuit having a control terminal electrically connected to a third scanning control signal line, a bias adjusting circuit having a control terminal electrically connected to a fourth scanning control signal line, and a light-emitting element reset circuit having an input terminal electrically connected to a second reset signal line, wherein the at least one first-type signal line comprises at least one of the light-emitting control signal line, the first scanning control signal line, the third scanning control signal line, or the fourth scanning control signal line; and the control signal line comprises the one second scanning control signal line
18/984,733 (claim 35)
18/984,756 (claims 33)
The display panel according to claim 11, wherein the at least one first-type signal line comprises a plurality of first-type signal lines, and the first-type driving circuit comprises a first-side driving circuit and a second-side driving circuit, wherein the display region is located between the first-side driving circuit and the second-side driving circuit in the first direction, one of the plurality of first-type signal lines is electrically connected to the first-side driving circuit, and another one of the plurality of at least one first-type signal lines is electrically connected to the second-side driving circuit.
The display panel according to claim 14, wherein the at least one first-type signal line comprises a plurality of first-type signal lines, and the first-type driving circuit comprises a first-side driving circuit and a second-side driving circuit, wherein the display region is located between the first-side driving circuit and the second-side driving circuit in the first direction, one of the plurality of first-type signal lines is electrically connected to the first-side driving circuit, and another one of the plurality of at least one first-type signal lines is electrically connected to the second-side driving circuit.
18/984,733 (claim 36)
18/984,756 (claims 34)
The display panel according to claim 35, wherein the first-side driving circuit comprises a first scanning control circuit and a light-emitting control circuit, wherein the first scanning control circuit is electrically connected to the first scanning control signal line, and the light-emitting control circuit is electrically connected to the light-emitting control signal line, and wherein the second-side driving circuit comprises a third scanning control circuit and a fourth scanning control circuit, wherein the third scanning control circuit is electrically connected to the third scanning control signal line, and the fourth scanning control circuit is electrically connected to the fourth scanning control signal line.
The display panel according to claim 33, wherein the first-side driving circuit comprises a first scanning control circuit and a light-emitting control circuit, wherein the first scanning control circuit is electrically connected to the first scanning control signal line, and the light-emitting control circuit is electrically connected to the light-emitting control signal line, and wherein the second-side driving circuit comprises a third scanning control circuit and a fourth scanning control circuit, wherein the third scanning control circuit is electrically connected to the third scanning control signal line, and the fourth scanning control circuit is electrically connected to the fourth scanning control signal line.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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