DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because the 2nd sentence, particularly the portion stating that a vector is divided into a singular sub-group, is grammatically incorrect. The examiner believes it would be more correct to say that a vector is divided into multiple sub-groups, or that a sub-group is obtained from a vector. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 11, replace “number of ALM” with --number of ALMs--.
In paragraph 11, 4th to last line, what does “it” refer to? Please amend for clarity.
In paragraph 16, the 1st sentence is grammatically incorrect and must be reworded. Also, please clarify what is separate from the computing device 102.
In paragraph 21, the 3rd sentence is grammatically incorrect and must be reworded.
In paragraph 25, line 4, re-locate “of vector A” from before the period to line 3 before “(or”.
In paragraph 26, line 3, what is the “0” in the middle of the vector?
In paragraph 29, last line, delete the space before the comma.
In paragraph 30, it appears that “Res_(n-1)/2” should be replaced with
--Res_(n/2)-- to match “202-n/2”. For example, for n=6, there would be three 2-bit subgroups (so bottom input would be Res_(6/2) = Res_3, instead of Res_2.5).
Paragraph 53 includes substantially similar language as the claims and should be corrected as the claims are corrected.
Anywhere applicant states that a vector is divided into a subgroup (singular) is grammatically incorrect for reasoning given above for the abstract.
Based on objections/112s below, any language in the specification/abstract/drawings should be corrected/clarified where appropriate.
Appropriate correction is required.
Drawings
The drawings are objected to because of the following minor informalities:
In FIG.2, it appears that the bottom input into AND 204 should be instead labeled --Res_(n/2)-- for similar reasoning given above with respect to paragraph 30.
In FIG.3, b0 is incorrectly connected to the A bus instead of the B bus. Similar mislabelings/misconnections also exist for a0, b1, and a1.
In FIG.4, step 402 is grammatically incorrect for similar reasoning given for the abstract.
FIGs.1 and 5 are objected to as failing to comply with 37 CFR 1.84(p)(4) because each of the following sets of reference characters are associated with the same respective component:
100 and 102; and
500 and 518.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
Claim 1 (and similarly claim 16) is objected to because of the following informalities:
Lines 4-5 are grammatically incorrect for reasons set forth above. Applicant could claim either dividing a first vector into a plurality of subgroups including a first n-bit subgroup (and similar for the second vector). Or, applicant could claim obtaining a first n-bit subgroup from a first vector (or the like).
Claim 4 (and similarly each of claims 9 and 17) is objected to because of the following informalities:
Lines 4-5 are grammatically incorrect for reasons set forth above, i.e. because applicant is claiming dividing the mask into a single third sub-group.
Claim 6 (and similarly claim 12) is objected to because of the following informalities:
Insert --the-- before “same”.
Claim 8 is objected to because of the following informalities:
Lines 2-3 are grammatically incorrect for reasons set forth above. Applicant could claim either dividing a first vector into a plurality of subgroups including a first n-bit subgroup (and similar for the second vector). Or, applicant could claim obtaining a first n-bit subgroup from a first vector (or the like).
In claim 8, lines 4-6, did applicant intend for the second applying to also be performed by the DSP blocks?. If so, the examiner recommends deleting “applying” in line 5.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations include:
In claim 1, “DSP blocks to implement a DSP-based mask operation, the DSP blocks configured to: divide…apply…subtract...; and output…”. While applicant shows DSP blocks in FIG.3 (302, 304), these blocks do not perform the claimed function. For instance, the vector is already divided prior to arriving at the DSP blocks. Thus, it is not clear what structure is actually doing the dividing. The DSP blocks also do not show applying a mask to a subgroup per se. Instead, masks appear to be applied, e.g. at 316, to a result of subtracting the sub-groups, e.g. at 310. Because the subtracting and outputting steps are depending on the dividing and applying, for which structure was not disclosed, it follows that structure for subtracting and output is also not disclosed. As such, broadest reasonable interpretation (BRI) is taken for the claimed blocks and 112(a)/(b) rejections appear below.
In claim 4, “the DSP blocks are further configured to divide the mask into a third n-bit subgroup” For similar reasoning laid out above, the examiner cannot find structure to implement these blocks. As such, BRI is taken and 112(a)/(b) rejections are set forth below.
In claims 5, 8, 11, 16-17, and 20, the examiner could similarly find no structure for the DSP blocks to perform the respective functions. Thus, BRI is taken and 112(a)/(b) rejections are set forth below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1, 4-5, 8, 11, 16-17, and 20, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the DSP blocks to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Applicant could claim “DSP block circuits” to not invoke 112(f).
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 4-5, 8, 11, 16-17, and 20, the DSP block + function limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 1, 4, and 16-17 are indefinite because they are inconsistent with the disclosure. These claims set forth that the DSP blocks divide the vectors/mask into subgroups. However, FIG.3 shows that the vectors/mask are divided into subgroups before the subgroups are sent to the DSP blocks 302,304. Thus, the DSP blocks appear to not actually do the dividing. This inconsistency renders the claim indefinite because it isn’t clear whether DSP blocks are actually performing the dividing operation. See MPEP 2173.03.
Claims 1, 8, and 16 are indefinite because they are inconsistent with the disclosure. These claims relate to applying the same mask to the same first and second sub-groups, subtracting the same two masked values, and outputting the same result of that subtraction. However, from FIGs.2-3, the same mask is not applied to the same subgroups. Instead, different mask bits are applied to different first and second sub-groups (e.g. FIG.3 shows block(s) 0 applying bits 0 and 1 of mask M to bits 0 and 1 of inputs A and B, whereas, from FIGs.2-3, block(s) 1 would apply bits 2 and 3 of mask M to bits 2 and 3 of inputs A and B, and so on for each block. This inconsistency renders the claims indefinite because it isn’t clear whether multiple blocks are being claimed to perform the exact same operations on the exact same data, or if each DSP block is applying its own respective mask, performing its own respective subtraction, and outputting its own respective result. The examiner is also confused what a DSP block is. Applicant shows two DSP blocks in FIG.3. Do these make up a single DSP block of FIG.2? See MPEP 2173.03.
Claims 1, 4-5, 7-8, 10-11, 13, 15-16, and 19-20 are indefinite because they are inconsistent with the disclosure. These claims set forth that the DSP blocks are configured to perform operations which appear to correspond to the equation in the last line of paragraph 21. However, based on paragraph 11, the described invention appears to convert the equation in the last line of paragraph 21, which is normally performed by lookup tables in ALMs/CLBs, to the equation in the last line of paragraph 27, which is to be performed by DSP blocks to increase utilization of DSP blocks within an FPGA during certain types of processing. FIG.3 in particular shows that DSP blocks are built to implement the exact equation of the last line of paragraph 27. As such, applicant’s DSP blocks do not appear to be performing the operations claimed (for instance, from FIG.3, there is no subtraction of one masked vector subgroup from another, i.e., the subtracting occurring at 306,308 precedes masking at 312,314). At most, the DSP blocks seem to be performing an equivalent of what is claimed (the equations in question generate the same results), but not what is claimed per se. This inconsistency renders the claim indefinite because it isn’t clear what the invented DSP blocks are actually performing.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 7, “the applying”, because there are two applying steps in claim 1.
In claim 13, “the applying” for similar reasoning.
All dependent claims are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the subject matter eligibility test in MPEP 2106, all claims are directed to a statutory category of invention.
Regarding claim 1:
With respect to step 2A (prong 1) of the test, the claim recites “divide a first vector into a first n-bit subgroup and a second vector into a second n-bit subgroup; apply a mask to the first n-bit subgroup to generate a first masked vector and apply the mask to the second n-bit subgroup to generate a second masked vector; subtract the second masked vector from the first masked vector to generate a result; and output the generated result.” Each of these operations can be performed in the human mind with or without the aid of pen and paper; therefore, the operations are classified in the category of mental processes. The applying, subtracting, and outputting are additionally, or alternatively, classified in the category of mathematical concepts, e.g. mathematical calculations, where applying a mask is Boolean algebra, and outputting a result of math is a necessary step of a mathematical calculation.
With respect to step 2A (prong 2) of the test, the claim recites additional elements including “a system comprising: a field-programmable gate array (FPGA) comprising digital signal processor (DSP) blocks to implement a DSP-based mask operator, the DSP blocks configured to” perform the claims operations. However, these are generic computing components claimed as a tool to perform an abstract idea. They also constitute a generic linking of the abstract idea in a particular technological (digital signal processing) environment. Per the courts, neither of these integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 6th and 8th bullets). Under an alternate interpretation than that taken above, “outputting the generate result” may be deemed as insignificant post-solution activity that is a nominal or tangential addition to the claim. Also per the courts, this does not integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 7th bullet).
With respect to step 2B of the test, the claim does not include additional elements, when considered individually and in combination, that are sufficient to amount to significantly more than the judicial exception because the claims include generic computing components that are used as a tool to implement the abstract idea and/or generically link the abstract idea to a DSP environment, neither of which amount to significantly more, per the courts (MPEP 2106.05(I)(A), 2nd enumerated list, items (i) and (iv)). Further, the outputting of the result is a well-understood, routine, conventional activity that does not amount to significantly more, per the courts (MPEP 2106.05(I)(A), 2nd enumerated list, items (ii)-(iii), and MPEP 2106.05(d)(II), items (i) (transmission of data) and (iv) (storing data)).
As such, claim 1 is not patent-eligible under 35 U.S.C. 101.
Referring to claim 2, applicant claims that the FPGA’s blocks are configured by moving masking operations associated with a CPU program or GPU shader to the blocks. These are again generic computing components and do not integrate or amount to significantly more, including in combination with additional elements of claim 1.
Referring to claim 3, applicant merely sets forth an association of the masking operations, which means the claim merely expands the abstract idea. There are no additional elements that could integrate or amount to significantly more.
Claim 4 merely sets forth more abstract idea(s) and, thus, the claim lacks additional elements that could integrate or amount to significantly more.
Claim 5 again sets forth only generic components (groups of two DSP blocks) to perform the abstract idea, which also amount to a generic link to a DSP environment. As stated above, such does not integrate or amount to significantly more.
Claims 6-7 again set forth only generic computing components and thus fail to integrate or amount to significantly more.
Claims 8-13 are not patent-eligible for similar reasoning as claims 1, 4, 4-7, respectively.
Claim 14 merely sets forth an association of the masking, which means the claim merely expands the abstract idea. There are no additional elements that could integrate or amount to significantly more.
Claim 15 sets forth determining steps, which are mental processes, i.e., abstract ideas. This claim does not set forth any additional element that could integrate or amount to significantly more.
Claim 16 is not patent-eligible for similar reasoning as claim 1, where a special purpose IC is even more generic than FPGA.
Claims 17-20 are not patent-eligible for similar reasoning as claims 4, 4, and 4-5, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over KronoTech, “Ladder Logic Masked comparison for Equal Instruction”, in view of the examiner’s taking of Official Notice.
Referring to claim 1, KronoTech has taught a system comprising: circuitry configured to:
divide a first vector into a first n-bit subgroup and a second vector into a second n-bit subgroup (N7 is a first vector (source) divided into four 4-bit counter subgroups. The second vector (compare) is divided into four corresponding 4-bit subgroups);
apply a mask to the first n-bit subgroup to generate a first masked vector and apply the mask to the second n-bit subgroup to generate a second masked vector (the mask in B3 is applied to the two subgroups to determine what to compare. For instance, in the first figure, the mask is set to 000Fh, which means that the entirety of the rightmost sub-groups of the two vectors are entirely compared);
KronoTech has not taught to subtract the second masked vector from the first masked vector to generate a result; and outputting the result. However, KronoTech has taught comparing values, and Official Notice is taken that performing comparison by subtracting was well-known in the art before applicant's invention. Subtracting a value from the same value results in 0. Thus, a subtraction result of 0 indicates the input values are the same, and a non-zero result indicates the input values are different. Subtraction is a trivial, fast computing operation and, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify KronoTech such that the comparison is implemented by subtracting the second masked vector from the first masked vector to generate and output a result.
KronoTech has also not taught a field-programmable gate array (FPGA) comprising digital signal processor (DSP) blocks to implement a DSP-based mask operator, the DSP blocks to perform the aforementioned steps. However, Official Notice is taken that such components were well-known in the art before applicant's invention. An FPGA is a re-programmable and flexible chip that allows for custom circuitry for processing to be implemented as desired. The reprogrammability also allows a programmer to upgrade, completely change, or otherwise modify a configuration as needed for increased efficiency. Additionally, a DSP is a known type of processor that is built to excel at high-speed continuous math operations instead of as a general-purpose processor. Applications that focus more on comparisons and math and don’t require general-purpose computing would be advantageously executed by a DSP to speed up processing. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify KronoTech such that the claimed steps are performed by DSP blocks to implement a DSP-based mask operator within an FPGA.
Referring to claim 2, KronoTech, as modified, has taught the system of claim 1, wherein the DSP blocks in the FPGA are configured by moving masking operations associated with a program running on a central processing unit (CPU) (in the combination proposed above, the masking operations could obviously be moved from a general-purpose CPU to a specialized DSP) or a shader running on a graphics processing unit (GPU) to the DSP blocks in the FPGA.
Referring to claim 3, KronoTech, as modified, has taught the system of claim 2, but has not taught wherein the masking operations are associated with one or more of: a computer vision application, a natural language processing application, and training a machine learning model. However, Official Notice is taken that these applications were well-known in the art (and well-known to include comparison) before applicant's invention. As a result, in order to increase flexibility and allow for KronoTech to be used in popular technical fields, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify KronoTech such that the masking operations are associated with one or more of: a computer vision application, a natural language processing application, and training a machine learning model.
Referring to claim 4, KronoTech, as modified, has taught the system of claim 1, wherein the DSP blocks are further configured to divide the mask into a third n-bit subgroup, wherein applying the mask to the first n-bit subgroup to generate the first masked vector comprises applying the third n-bit subgroup to the first n-bit subgroup to generate the first masked vector and applying the mask to the second n-bit subgroup to generate the second masked vector comprises applying the third n-bit subgroup to the second n-bit subgroup to generate the second masked vector (KronoTech similarly has a mask whose 4-bit subgroups correspond to the 4-bit counter values). KronoTech has not taught wherein a value of n in the first n-bit subgroup, the second n-bit subgroup, and the third n-bit subgroup is two. However, changing the size of ‘n’ is deemed a routine expedient and not a patentable distinction. See MPEP 2144.04, including section (IV)(A). One could have implemented 2-bit counters in KronoTech as easily as 4-bit counters and yielded similar results (the comparison would work the same only at finer granularity). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify KronoTech such that a value of n in the first n-bit subgroup, the second n-bit subgroup, and the third n-bit subgroup is two.
Referring to claim 5, KronoTech, as modified, has taught the system of claim 4, wherein applying the third n-bit subgroup to the first n-bit subgroup to generate the first masked vector is performed using a first group of two DSP blocks and applying the third n-bit subgroup to the second n-bit subgroup to generate the second masked vector is performed using a second group of two DSP blocks (two perform subtraction with two values, the two bit values are presented to an ALU/subtractor in full. Thus, each bit must be appropriately set in parallel by the mask logic. As such, there is a DSP block for each bit, so an 2-bit subgroup requires two DSP blocks).
Referring to claim 6, KronoTech, as modified, has taught the system of claim 5, wherein the first group of two DSP blocks and the second group of two DSP blocks are different or same (as different or same encompasses all possible permutations, one of them must be present in KronoTech).
Referring to claim 7, KronoTech, as modified, has taught the system of claim 1, wherein the DSP blocks in the FPGA are programmed with a configuration file to perform the dividing, the applying, the subtracting, and the outputting operations (this is how an FPGA works, where blocks are programmed with a configuration file to perform the desired operations).
Claim 8 is rejected for similar reasoning as claim 1
Claim 9 is rejected for a subset of reasoning set forth in the rejection of claim 4.
Claim 10 is rejected for similar reasoning as claim 4.
Claims 11-13 are rejected for similar reasoning as claims 5-7, respectively.
Claim 14 is rejected for similar reasoning as claim 3, where Official Notice is taken that a machine learning task (and comparisons thereof) were well-known in the art before applicant’s invention.
Claim 15 is rejected for a subset of reasoning set forth in the rejection of claim 1.
Claim 16 is rejected for most of the reasoning set forth in the rejection of claim 1, where an FPGA is deemed a special-purpose IC. However, note that claim 16 does not require that the comparison be performed by subtracting. KronoTech alone teaches comparing. Thus, Official Notice is not relied on to teach subtracting in this rejection.
Claims 17-18 are rejected for a subset of reasoning set forth in the rejection of claim 4.
Claims 19-20 are rejected for similar reasoning as claims 4-5, respectively.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
YouTube has taught “Bit Masking Tutorial - MEQ | Masked Equals Instruction PLC Programming Bit Manipulation Optimization”. In this video, starting at approximately 6:16, the MEQ instruction is shown in an example that compares whether desired valves are open, where each bit of a source corresponds to different valve, and each bit of another source corresponds to an open/closed status of a valve. A mask is set to determine which valves to check for open status, and only those bits of the vectors are checked.
Eapen (US 2024/0028337) has taught an instruction that applies a mask to a vector source and a CompTarget, and to compare the unmasked portions to generate a result (e.g. FIGs.3,5,7).
Divr (WO 2007/083199) has taught fetching multiple chunks of data, selecting masking chunks, and then comparing valid data chunks,
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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