DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II and Species III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/10/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noda et al. (US 2024/0053903 A1).
Regarding claim 1, Noda teaches a method performed by a storage device, the method comprising:
receiving, from a host device, a write command (Fig. 1, memory system 1 receives a write command from the host device 2);
performing a first write operation to write a first set of data on a first word line (Fig. 13, the memory will write a first set of data to a first word line WL0) of a block in a plurality of blocks included in a virtual block (Fig. 15A, virtual block includes a plurality of memory blocks);
identifying a program error associated with the first write operation on the first word line (“identifying a program error” is interpreted as a step to determine whether there is an error in write operation. During the program operation, the memory device will perform an inherent verify operation to determine if the memory cells are programmed to the correct threshold voltage to represent the data); and
performing a second write operation to write a second set of data on a second word line of the block (Fig. 13, the memory will write a second set of data to a second word line WL3).
Regarding claim 2, Noda teaches the method of claim 1, wherein the second word line is separated from the first word line by a quantity of word lines (Fig. 13, word lines WL1 and WL3 are between the first word line WL0 and second word line WL3).
Regarding claim 5, Noda further teaches the method of claim 1, wherein the block in the plurality of blocks is a first block, the method comprising performing a write operation on a word line of a second block in the plurality of blocks, wherein the word line of the second block is associated with a word line index that corresponds to the first word line (¶0112 to ¶0116).
Regarding claim 9, Noda further teaches the method of claim 1, comprising:
scanning a previous wordline within the block based at least in part on identifying the program error; identifying no program error on the previous word line; and maintaining data on the previous word line based at least in part on identifying no program error on the previous word line (after each program operation, an inherent verify operation is performed to check if the data have been programmed correctly. If it is determined that the previous data was programmed correctly, the data will be maintained in the previous wordline).
Regarding claim 11, Noda further teaches the method of claim 1, wherein the second set of data is the same as the first set of data (Fig. 13, in a memory device a word line can have 128 bitlines, which the word line can store a set of data up to 128 bits. These days, an image can be more than 3MB of data which will be stored across multiple word lines. Therefore, a set of data can be written across multiple word lines, which the first and second set of data can be part of the same set of data).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noda as applied to claim 1 above, and further in view of Jung et al. (US 2015/0113342 A1).
Regarding claim 3, Noda is silent in teaching writing dummy data to one or more word lines between the first word line and the second word line.
Jung teaches writing dummy data to one or more word lines between the first word line and the second word line (¶0069) .
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to write dummy date to a word line during sudden power-off (SPO) in order to use the dummy date to perform repair algorithm for correcting an error in the read data.
Regarding claim 4, Noda further teaches the method of claim 3, wherein performing the second write operation on the second word line of the block is based at least in part on detecting no program error associated with the writing of dummy data on at least a last word line of the one or more word lines (Fig. 13, when the memory device does not detect any errors, it will perform the program operation in sequence through the word lines).
Claim(s) 6-8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noda as applied to claim 1 above, and further in view of Kim (US 2021/0193227 A1).
Regarding claim 6, Noda does not explicitly teach wherein the virtual block is a first virtual block, the method comprising: scanning a previous word line within the block based at least in part on identifying the program error; identifying a scan read error on the previous word line; and writing data associated with the previous word line on a second virtual block based at least in part on the scan read error.
Kim teaches wherein the virtual block is a first virtual block, the method comprising: scanning a previous word line within the block based at least in part on identifying the program error; identifying a scan read error on the previous word line; and writing data associated with the previous word line on a second virtual block based at least in part on the scan read error (memory device will check whether the first PAGE1 is defective. If it is determined it is defective, the controller will try program the data into the second page and the third page before the controller determines the whole memory block is defective and programing the data into a second non-defective block, see ¶0029 to ¶0031).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to verify the program data is programmed correctly into the memory device and if an error occurred, the memory device will program it into a non-defective area in order to program the data successfully.
Regarding claim 7, Kim and Nod further teach method of claim 6, wherein a second plurality of blocks is included in the second virtual block, wherein writing the data associated with the previous word line on the second virtual block comprises: writing the data associated with the previous word line on a third word line of a third block in the second plurality of blocks (memory device includes a plurality of memory block. If the memory device determines one of the blocks is defective, the memory device still has other memory blocks to write the data, Kim Fig. 1 and ¶0036).
Regarding claim 8, Noda and Kim further teach the method of claim 6, comprising: moving, to the second virtual block and based at least in part on identifying the scan read error on the previous word line, data written to the multiple of the plurality of blocks of the first virtual block (memory device includes a plurality of memory block. If the memory device determines one of the blocks is defective, the memory device still has other memory blocks to write the data, Kim Fig. 1 and ¶0036).
Regarding claim 10, it is well-know in the art that a memory device will mark a block defective, if the block had a plurality of errors above a certain threshold. To expedite the prosecution of this case Kim is used to teach the claimed limitation.
Noda did not explicitly teach wherein the virtual block is a first virtual block, the method comprising: identifying, after performing the write operation second write operation on the second word line of the first virtual block, a quantity of program errors on the first virtual block; and moving, to a second virtual block, data written to the virtual block at multiple blocks multiple of the plurality of blocks of the first virtual block.
Kim teaches identifying, after performing the write operation second write operation on the second word line of the first virtual block, a quantity of program errors on the first virtual block; and moving, to a second virtual block, data written to the virtual block at multiple blocks multiple of the plurality of blocks of the first virtual block (memory device will check whether the first PAGE1 is defective. If it is determined it is defective, the controller will try program the data into the second page and the third page before the controller determines the whole memory block is defective and programing the data into a second non-defective block, see ¶0029 to ¶0031).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to mark a block defective and write data into another block in order to protect the user data from getting lost if the data is written into a bad block.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
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