Prosecution Insights
Last updated: August 15, 2026
Application No. 18/985,337

CONTROL CIRCUIT AND SWITCHING POWER SUPPLY

Non-Final OA §102§103
Filed
Dec 18, 2024
Priority
Dec 28, 2023 — CN 202311846079.5
Examiner
PEREZ, BRYAN REYNALDO
Art Unit
Tech Center
Assignee
Silergy Semiconductor Technology (Hangzhou) Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
620 granted / 738 resolved
+24.0% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
29 currently pending
Career history
757
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
33.1%
-6.9% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This non-final office action is responsive to Applicants' application filed on 12/18/24. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4,12,14-16,20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al. (US 20220209673 A1) Regarding claim 1. Guo teaches a control circuit [20] for a switching power supply [fig 2, 10], the control circuit being configured to: a) obtain a switching frequency [see inputs of 26] of a power transistor [i.e. 11] in the switching power supply in a sampling period [fig 8, Vfb]; b) adjust an on-time [26] of the power transistor to regulate a switching period of the power transistor to decrease a difference between the switching frequency and an expected switching frequency [adjusting the on-time in a COT regulates the switching frequency per ( f s w =   1 t o n + t o f f ), one of ordinary skill in the art expect adjusting switching frequency per adjusting the on-time]; and c) wherein the sampling period is greater than the switching period of the power transistor [see in fig 8, 201; Vfb have longer periods than Turnon_S]. Regarding claim 2. Guo teaches the control circuit of claim 1, wherein the on-time is adjusted independent of a control loop [26 is independent of Vfb] in at least one sampling period in accordance with a size relationship between the switching frequency and the expected switching frequency. Regarding claim 3. Guo teaches the control circuit of claim 2, wherein: a) when the switching frequency is less than the expected switching frequency, the on-time is decreased by at least one step every other at least one sampling period [¶9-¶10]; and b) when the switching frequency is greater than the expected switching frequency, the on-time is increased by at least one step every other at least one sampling period [¶9-¶10]. Regarding claim 4. Guo teaches the control circuit of claim 1, wherein: a) when the switching frequency exceeds an upper limit of the expected switching frequency, the switching period of the power transistor is increased [¶9, postponing off time extends the on time]; and b) when the switching frequency is lower than a lower limit of the expected switching frequency, the switching period of the power transistor is decreased [¶9-¶10], such that the switching period of the power transistor is within a range of the expected switching frequency [target limit, ¶5]. Regarding claim 12. Guo teaches a switching power supply, comprising the control circuit of claim 1, and further comprising a power stage circuit [power stage of 10]. Regarding method claims 14-16,20, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5, 8-11,17 rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20220209673 A1) in view of Fesler et al. (US 11290090 B2) Regarding claim 5. Guo teaches the control circuit of claim 1. However, Guo does not explicitly mention further comprising an adaptive on-time circuit configured to count pulses of a switching control signal for controlling the power transistor within the sampling period to obtain the switching frequency, and to adjust the on-time of the power transistor based on a comparison result between the switching frequency and the expected switching frequency. Fesler teaches a circuit comprising: an adaptive on-time circuit [fig 3] configured to count pulses [308] of a switching control signal for controlling the power transistor within the sampling period [i.e. withing feedback T] to obtain the switching frequency, and to adjust the on-time of the power transistor based on a comparison result [320] between the switching frequency and the expected switching frequency It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Fesler in order to provide a circuit that prevents the off-time from inadvertently reaching or falling below the minimum off-time, any potential problems associated with inadequate control stability or insufficient time for making correct decisions during the off-time, among other potential problems, are avoided [col 2 lines 40-45]. Regarding claim 8. Guo teaches the control circuit of claim 3, wherein a time of one step is less than the on-time of the power transistor [see fig 8a Vcs_S is less than Turnon_S]. Regarding claim 9. Guo teaches the control circuit of claim 5, further comprising a PWM generation circuit [22] configured to receive the on-time and a trigger signal, and to generate the switching control signal of the power transistor accordingly, wherein the trigger signal is configured to set the switching control signal [function of 22]. Regarding claim 10. Guo teaches the control circuit of claim 5, wherein the adaptive on-time circuit comprises: a) a counter [263, fig 4] configured to obtain the switching frequency according to a sampling clock signal characterizing the sampling period and the switching control signal, and compare [261] the switching frequency against the expected switching frequency to obtain the comparison result; and b) an on-time adjustment circuit [262] configured to calculate the on-time according to an input voltage and an output voltage [function of circuit is based on Vin and Vout] of the switching power supply, and to adjust the on-time of the power transistor according to the comparison result [delta f]. Regarding claim 11. Guo teaches the control circuit of claim 10, wherein the on-time of the power transistor has a same changing trend as the output voltage, and an opposite changing trend as the input voltage [duty ratio follows trend of output voltage and opposite to vin since Vin is not being regulated]. Regarding method claims 17, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. Claims 6,18 rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20220209673 A1) Regarding claim 6. Guo teaches the control circuit of claim 1, except for wherein a duration of the sampling period is at least 10 times a duration of the switching period. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify a specific threshold value which would better align the circuit towards design requirements, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. Regarding method claims 18, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. Allowable Subject Matter Claims 7,13,19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome. Examiner Note The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /BRYAN R PEREZ/Examiner, Art Unit 2838
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Prosecution Timeline

Dec 18, 2024
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
98%
With Interview (+13.8%)
2y 3m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

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