DETAILED ACTION
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 35-40 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claims 35-40 are directed to a processor configured to... However, under the broadest reasonable interpretation, the claims do not recite any tangible structural elements as the claimed elements of claims 35-40 includes nothing more than sets of software instructions or a system containing only software element (e.g., a software processor). Therefore the claimed subject matter as a whole fails to fall within a statutory subject matter as software per se is not to a process, machine, manufacture, or composition of matter within the meaning of 35 USC 101.
In general, system claims will be considered statutory under § 101 as long as the system claim contains at least one element to be implemented as hardware. Thus claims 35-40 will be considered statutory only if at least one of the claimed modules is implemented as some hardware element. When system claims are written such that its elements may be implemented as purely software components, then the system is no longer a machine but software per se. Software per se is judged to be non-statutory subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hugosson et al. (US20190246117A1).
Regarding claim 21, Hugosson discloses a system comprising (para [0083] shows a video decoder);
at least one processor; and a non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate the at least one processor to (para [0139]):
receive a portion [a plurality of independent segments] of an encoded bitstream (para [0034] shows receiving an encoded data stream including a plurality of independent segments each of which can be decoded independently and a header containing information indicative of the location of each of the plurality of independent segments within the data stream; para [0050] shows markers may be inserted into the data stream to indicate the beginning of each of the independent segments; para [0052] shows the header may indicate the locations of the independent segments within the data stream by indicating (e.g. by pointing to) the locations of these markers; para [0128] shows the encoded data is then bit-aligned with the marker);
decode a first segment of the encoded bitstream based on a first fence identifier [marker] associated with the encoded bitstream, wherein the first segment is independent from other portions of the encoded bitstream, wherein the first fence identifier does not correspond to the other portions of the encoded bitstream (para [0034] shows receiving an encoded data stream including a plurality of independent segments each of which can be decoded independently and a header containing information indicative of the location of each of the plurality of independent segments within the data stream; para [0073] shows the independent segments in the data stream are defined using a marker; para [0128] shows the encoded data is then bit-aligned with the marker), and
wherein the first segment is decoded independent of receiving the other portions of the encoded bitstream; and indicate, using the first fence identifier, that decoding the first segment is complete (para [0080] shows the decoder, upon receipt of a plurality of independent segments each of which can be decoded independently and a header containing information indicative of the location of each of the independent segments, is thus able to read the custom header to identify the locations of the plurality of independent segments, and thereby decode the segments; para [0123] shows the independent segments defined by the markers 22 may thus be immediately allocated to a decoding core and put out for decoding entirely independently of one another; para [0134] shows the segment is then processed by the core and the decoded data is written out to the output image buffer 802.)
Regarding claim 22, Hugosson as applied to claim 21 discloses the set of executable instructions is to manipulate the at least one processor to: write the decoded first segment to a stream buffer that is accessible by an image processor (para [0134] shows the segment is then processed by the core and the decoded data is written out to the output image buffer 802; para [0138] shows an image/video processor 2080.)
Regarding claim 23, Hugosson as applied to claim 22 discloses the set of executable instructions is to manipulate the at least one processor to: perform image processing operations on the first segment written to the stream buffer without performing the image processing operations on the other portions of the encoded bitstream (para [0030] shows each of the independent segments identified from the custom header can be immediately allocated to a respective buffer/core of the decoder, and each of the independent segments can be decoded independently of one another; para [0134] shows the segment is then processed by the core and the decoded data is written out to the output image buffer 802.)
Regarding claim 24, Hugosson as applied to claim 21 discloses the portion of the encoded bitstream is to include some but not all of an image frame (para [0026] shows an encoded data stream comprising: a plurality of independent segments, each segment encoding part of an array of data element; para [0040] shows the array(s) of data elements or positions may correspond to all or part of a desired image.)
Regarding claim 25, Hugosson as applied to claim 21 discloses the set of executable instructions is to manipulate the at least one processor to: subsequent to decoding the first segment, decode a second segment of the encoded bitstream based on a second fence identifier associated with the encoded bitstream, wherein the second segment is independent from other portions of the encoded bitstream, and wherein the second fence identifier does not correspond to the other portions of the encoded bitstream (para [0030] shows each of the independent segments identified from the custom header can be immediately allocated to a respective buffer/core of the decoder, and each of the independent segments can be decoded independently of one another; para [0050] shows markers may be inserted into the data stream to indicate the beginning of each of the independent segments.)
Regarding claim 26, Hugosson as applied to claim 21 discloses the set of executable instructions is to manipulate the at least one processor to:
receive a second portion of the encoded bitstream; and subsequent to decoding the first segment, decode a second segment based on a second fence identifier associated with the encoded bitstream, wherein the second segment is independent from other portions of the encoded bitstream including the first segment, and wherein the second fence identifier does not correspond to the other portions of the encoded bitstream (para [0030] shows each of the independent segments identified from the custom header can be immediately allocated to a respective buffer/core of the decoder, and each of the independent segments can be decoded independently of one another; para [0050] shows markers may be inserted into the data stream to indicate the beginning of each of the independent segments; para [0080] shows the decoder, upon receipt of a plurality of independent segments each of which can be decoded independently and a header containing information indicative of the location of each of the independent segments, is thus able to read the custom header to identify the locations of the plurality of independent segments, and thereby decode the segments).
Regarding claim 27, Hugosson as applied to claim 21 discloses indicating, using the first fence identifier, that decoding the first segment is complete comprises: modifying the first fence identifier (para [0050] shows the markers may generally comprise synchronisation or restart markers that act to delimit the different segments by breaking any processing dependencies between blocks of data elements in the encoded data stream; the independent segments may be defined by inserting synchronisation or restart markers into the data stream that act to reset the predictor variables used in the encoding scheme.)
Regarding claims 28-34, claims 28-34 are method claims. These method claims require limitations that are similar to those recited in the system claims 21-27 to carry out the method steps. And since Hugosson anticipates the system that carries out the method including limitations required to carry out the method steps, therefore method claims 28-34 would have also been anticipated by Hugosson.
Regarding claims 35-40, claims 35-40 are directed to a processor. Claims 35-40 require limitations that are similar to those recited in the system claims 21-26 to carry out the method steps. And since Hugosson anticipates the system that carries out the method including limitations required to carry out the method steps, therefore method claims 35-40 would have also been anticipated by Hugosson.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Baeza et al. (US20090002379A1) discloses in para [0160] a decoder includes a module that parses encoded video bit streams to discover segments that can be independently decoded; para [0523] shows the CPU and GPU maintain synchronization, for example, using “fences.” A fence is a marker inserted into the command buffer by the CPU. The fence is triggered once the GPU reaches it. Synchronization helps the CPU track when a picture has been completely processed by the GPU in order to reuse resources and output the picture, subject to display ordering constraints. When a fence is signaled, the picture has been completely decoded.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/TAN DOAN/Primary Examiner, Art Unit 2442
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