DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 5/20/2026, in view of amendments, have been fully considered but they are not persuasive: see rejection below for mapping new limitations to the reference.
Allowable Subject Matter
Claims 4, 8, 13, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and all 35 USC § 101 rejections are overcome.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-12, 14-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ioannou (US 2019/0171381 A1).
For claim 1, Ioannou teaches a memory system, comprising: one or more processors configured to: perform a first read procedure associated with a first memory stripe, wherein the first memory stripe includes a logical group of (a memory stripe is a logical group) multiple data storage elements associated with a parity check payload (“associated” is a loose connection: two items are associated with each other just by being in the same system; parity is already part of RAID which is in the system), and wherein the first memory stripe is associated with one or more error correction elements; identify a first read error associated with the first read procedure, wherein the first read error is associated with a first data storage element, of the multiple data storage elements of the first memory stripe (all memory elements are part of a stripe and only one is declared); perform a first read error recovery procedure using the parity bits of the one or more error correction elements; (recovery in RAID is always using parity; see [0019], [0030], [0006], and other locations the system is a RAID system having multiple (many) storage elements; it uses parity thus it’s RAID level 3 and above; in normal operation of RAID 3, by definition, errors in stripes are detected and corrected using the parity block of the stripe) perform a second read procedure associated with the first memory stripe; identify a second read error associated with the second read procedure, wherein the second read error is associated with a second data storage element, of the multiple data storage elements, that is a different data storage element than the first data storage element; (more than one spontaneous error can appear in any storage element, and there is no control over when and where errors can appear; see locations pointed to above: this is still standard RAID operation, as reads are performed continuously; a stripe is spread over multiple disks, so a read from a stripe is designed to be a read from different disks. see [0005] and other locations: the number of errors are counted per memory unit/stripe, thus there are multiple reads per stripe) and perform a second read error recovery procedure using the one or more error correction element (recovery in RAID is always using paritysee above: standard RAID operations).
For claim 2, Ioannou teaches the limitations of claim 1 for the reasons above and further teaches the first read error recovery procedure and the second read error recovery procedure are associated with a redundant-array-of-independent-disks read error recovery procedure (see locations pointed to above).
For claim 3, Ioannou teaches the limitations of claim 1 for the reasons above and further teaches the one or more components, to perform the first read error recovery procedure, are configured to use a first payload associated with a first error correction element, of the one or more error correction elements, and wherein the one or more components, to perform the second read error recovery procedure, are configured to use a second payload associated with the first error correction element (see [0030-0031] and other locations: view parity for a stripe as said payload; RAID 6 has two different parities/payloads).
For claim 5, Ioannou teaches the limitations of claim 1 for the reasons above and further teaches the one or more components, to perform the first read error recovery procedure, are configured to use a first payload associated with a first error correction element, of the one or more error correction elements, and wherein the one or more components, to perform the second read error recovery procedure, are configured to use a second payload associated with a second error correction element, of the one or more error correction elements (see [0030-0031] and other locations: different parity disks for different stripes; standard RAID).
For claim 6, Ioannou teaches the limitations of claim 5 for the reasons above and further teaches the one or more components are further configured to write data associated with the first data storage element to the first error correction element based on identifying the first read error (see [0030-0031] and other locations: standard RAID; this occurs when the read error is from the parity disk; in this case parity disk is corrected/written into based on the other disks, which are non-parity disks in case of RAID 3 to5).
For claim 7, Ioannou teaches the limitations of claim 5 for the reasons above and further teaches the first memory stripe includes the first error correction element, and wherein a second memory stripe, different than the first memory stripe, includes the second error correction element (see [0030-0031] and other locations: standard RAID; different stripes, different parity disks).
For claim 9, Ioannou teaches the limitations of claim 5 for the reasons above and further teaches the one or more components are further configured to: perform a third read procedure associated with the second memory stripe; identify a third read error associated with the third read procedure; and perform a third read error recovery procedure using the second payload (see locations pointed to above: still standard RAID, reads are continuous, and corrections are continuous).
For claims 10-12, 14-16, and 18, the claims recite essentially similar limitationsas claims 1-3, 5-7, and 9 respectively. Claims 10-12, 14-16, and 18 are a method
For claims 19-20, the claims recite essentially similar limitations as claims 1-2 respectively. Claims 19-20 are a medium
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114
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