DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-8, 10-15 and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20250061955 to Yoo et al. (“Yoo”).
A to claim 1, Yoo teaches A non-volatile memory apparatus (As found in at least FIGS. 1-3 and at least [0013]), comprising: a plurality of memory cells arranged in a plurality of memory strings (As found in at least FIG. 2); a plurality of word lines connected to the plurality of memory cells (As found in at least FIG. 2: WL#); a plurality of bit lines connected to the plurality of memory strings (As found in at least FIG. 2: BL#); and a control circuit connected to the plurality of word lines and the plurality of bit lines, the control circuit configured to program data in a memory storage area by (As found in at least FIGS. 1A-1B: control circuit; and at least [0011]): programming a first set of memory cells in the memory storage area with a first subset of the data using a first program mode, the first program mode including performing a plurality of program-verify iterations to establish a baseline program voltage (As found in at least FIGS. 12-13 and at least [0089-0090]: disclosed are 3 program-verify) ; and programming a second set of memory cells in the memory storage area with a second subset of the data using a second program mode, the second program mode including performing a single program iteration based on the baseline program voltage (As found in at least FIGS. 12-13 and at least [0089-0090]: VPGM or VPGM plus a configurable offset is set to SV_VPGM and is stored in the NAND register of the chip. If other strings and word lines in the same memory block are subsequently programmed, then the initial programming voltage in the first program loop of those subsequent programming operations is set to SV_VPGM, thereby improving performance by skipping unnecessary program loops without overprogramming the memory cells).
As to claim 3, Yoo teaches wherein the first set of memory cells and the second set of memory cells are in a same memory layer and a same memory string within the memory storage area and the second program mode includes using a program voltage that is equal to the baseline program voltage (As found in at least FIGS. 1-4 and at least [0089-0090]: and VPGM or VPGM plus a configurable offset is set to SV_VPGM).
As to claim 4, Yoo teaches wherein the first set of memory cells and the second set of memory cells are in a same memory layer but different memory strings within the memory storage area and the second program mode includes using a program voltage that is equal to the baseline program voltage plus a string-level offset (As found in at least FIGS. 1-4 and at least [0089-0090]: and VPGM or VPGM plus a configurable offset is set to SV_VPGM).
As to claim 5, Yoo teaches wherein the first set of memory cells and the second set of memory cells are in different memory layers within the memory storage area and the second program mode includes using a program voltage that is equal to the baseline program voltage plus a layer-level offset (As found in at least FIG. 6B, different memory layers in the vertical; and as found in at least [0089-0090]).
As to claim 6, Yoo teaches wherein the plurality of program-verify iterations includes two program pulses and one verify pulse (As found in at least FIGS. 11-12: there are disclosed program-verify iterations including two program pulses an one verify pulse).
As to claim 7, Yoo wherein the first subset of the data corresponds to a first page of the data that is programmed (As found in at least [0022-0024] and [0033]: a page to be programmed).
As to claim 8, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
As to claim 10, see rejection to at least claim 3.
As to claim 11, see rejection to at least claim 4.
As to claim 12, see rejection to at least claim 5.
As to claim 13, see rejection to at least claim 6.
As to claim 14, see rejection to at least claim 7.
As to claim 15, see rejection to at least claim 1.
As to claim 17, see rejection to at least claim 3.
As to claim 18, see rejection to at least claim 4.
As to claim 19, see rejection to at least claim 5.
As to claim 20, see rejection to at least claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250061955 to Yoo et al. (“Yoo”) in view of U.S. Patent/Publication No. 20240071531 to Iwasaki et al. (“Iwasaki”).
As to claim 2, while Yoo teaches substantially the claimed invention, the teachings may not expressly include: wherein the second program mode further includes applying a program voltage that is equal to the baseline program voltage plus an offset and a value of the offset depends on a physical location of the second set of memory cells in the memory storage area relative to the first set of memory cells.
However, relevantly and complementarily, Iwasaki teaches wherein the second program mode further includes applying a program voltage that is equal to the baseline program voltage plus an offset and a value of the offset depends on a physical location of the second set of memory cells in the memory storage area relative to the first set of memory cells (As found in at least [0089]: different program verify offsets may be used based on the access line location within the memory array).
Yoo and Iwasaki are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having program-verify operations.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Yoo as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Iwasaki also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: it is well-known and well-understood in the relevant art of semiconductor devices that within a device, a chip, an integrated circuit (IC) --whatever name one may want to use – because of manufacturing non-idealities, different areas of the chip have different responses to electrical operations; some areas may be more affected due to power fluctuations, or temperature gradients or process variations.
Therefore, it would have been obvious to combine Yoo with Iwasaki to make the above modification.
As to claim 9, see rejection to at least claim 2.
As to claim 16, see rejection to at least claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
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