DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 is objected to because of the following informalities:
The word “to” should be inserted after “a resume command” in claim 9, line 2. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The recitation of “wherein the control circuit is further configured to perform the second verify operation for the plurality of memory cells independent of the second program loop.” In claim 19 is confusing. Since the second verify operation happens before the program operation of the second loop, the second verify operation cannot depend on the second program loop.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 12,198,764. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2-21 would have been obvious over claim 11 of the patent.
Regarding claims 2, 9-12, 16-18 and 21, claim 11 of the patent recites a non-volatile memory device comprising:
a plurality of memory cells stacked on a substrate in a vertical direction (claim 11, lines 2-3) and connected to a plurality of word lines and a plurality of bit lines; and
a control circuit (claim 11, line 6) configured to
receive a program command (claim 1, line 7),
in response to the program command, perform a first program loop of a program operation on the plurality of memory cells by applying a first voltage to a selected word line of the plurality of word lines (claim 11, lines 10-12),
verify the plurality of memory cells by applying a second voltage to the selected word line of the plurality of word lines in response to the program command (claim 11, lines 13-14), and
receive a suspend command,
enter a suspend state,
receive a resume command (claim 11, line 24), and
in response to the program command, perform a second program loop of the program operation on the plurality of memory cells by applying a fourth voltage to the selected word line of the plurality of word lines (claim 11, lines 25-28).
It would have been obvious to one having ordinary skill in the art to recognize that the non-volatile memory device and the memory system of claims 2, 9-12, 16-18 and 21 and the non-volatile memory device of claim 11 are identical in structure; therefore, the differences between claims 2, 9-12, 16-18 and 21 and claim 1 of the patent are only functional limitations.
Regarding claim 3, claim 11 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to enter the suspend state after verifying the plurality of memory cells by applying the second voltage to the selected word line and before verifying the plurality of memory cells by applying the third voltage to the selected word line.
Regarding claim 4, claim 11 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify (claim 11, line 21 output read data) the plurality of memory cells by applying the third voltage to the selected word line before performing the second program loop of the program operation on the plurality of memory cells.
Regarding claim 5, claim 11 recites the non-volatile memory device of claim 2, wherein in response to receiving the suspend command during performing the first program loop of the program operation on the plurality of memory cells, the control circuit is further configured to enter the suspend state (claim 11, line 19) after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line (claim 11, lines 13-14).
Regarding claim 6, claim 11 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the second voltage to the selected word line to check a state of the plurality of memory cells after performing the first program loop of the program operation on the plurality of memory cells.
Regarding claim 7, claim 11 of the patent recites the non-volatile memory device of claim 6, wherein in response to receiving the suspend command during verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells, the control circuit is further configured to enter the suspend state (claim 11, line 19) after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells (claim 11, lines 13-14).
Regarding claim 8, claim 11 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to read data (claim 11, line 21) from the plurality of memory cells in the suspend state.
Regarding claim 13, claim 11 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to perform the first and second verify operation (claim 11, lines 12-13 and lines 19-23) for the plurality of memory cells between the first program loop and the second program loop.
Regarding claim 14, claim 11 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to perform the second verify operation for the plurality of memory cells independent of the second program loop.
Regarding claim 15, claim 11 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to read data from the plurality of memory cells in the suspend state (claim 11, lines 20-23).
Regarding claim 19, claim 11 of the patent recites the memory system of claim 18, wherein the memory controller is configured to transmit a resume command the non-volatile memory device, and the non-volatile memory device is further configured to perform the second verify operation for the plurality of memory cells in response to receiving the resume command.
Regarding claim 20, claim 11 of the patent recites the memory system of claim 18, wherein the non-volatile memory device is further configured to read data from the plurality of memory cells in the suspend state (claim 11, lines 20-23).
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,830,554. Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one having ordinary skill in the art to recognize that the non-volatile memory device and the memory system of claims 2-21 are used to perform the method of claims 1-20 of the patent.
Regarding claims 2, 11 and 18, claim 1 of the patent recites a non-volatile memory device comprising:
a plurality of memory cells stacked on a substrate in a vertical direction and connected to a plurality of word lines and a plurality of bit lines (claim 1, lines 1-4); and
a control circuit (claim 1, lines 4-5) configured to
receive a program command (claim 1, line 7),
in response to the program command, perform a first program loop of a program operation on the plurality of memory cells by applying a first voltage to a selected word line of the plurality of word lines (claim 1, lines 8-13),
verify the plurality of memory cells by applying a second voltage to the selected word line of the plurality of word lines in response to the program command (claim 1, lines 14-15), and
receive a suspend command (claim 1, line 20),
enter a suspend state (claim 1, line 24)
receive a resume command (claim 1, line 26),
verify the plurality of memory cells by applying a third voltage to the selected word line of the plurality of word lines in response to the resume command (claim 4), and
in response to the program command, perform a second program loop of the program operation on the plurality of memory cells by applying a fourth voltage to the selected word line of the plurality of word lines (claim 1, lines 16-19).
Regarding claim 3, claims 1 and 4 of the patent recite the non-volatile memory device of claim 2, wherein the control circuit is further configured to enter the suspend state claim 1, line 24) after verifying the plurality of memory cells by applying the second voltage to the selected word line (claim 1, lines 14-15) and before verifying the plurality of memory cells by applying the third voltage to the selected word line (claim 4).
Regarding claim 4, claim 1 recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the third voltage to the selected word line before performing the second program loop of the program operation on the plurality of memory cells.
Regarding claim 5, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein in response to receiving the suspend command during performing the first program loop of the program operation on the plurality of memory cells, the control circuit is further configured to enter the suspend state after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line.
Regarding claim 6, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the second voltage to the selected word line to check a state of the plurality of memory cells after performing the first program loop of the program operation on the plurality of memory cells.
Regarding claim 7, claim 1 of the patent recites the non-volatile memory device of claim 6, wherein in response to receiving the suspend command during verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells, the control circuit is further configured to enter the suspend state after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells.
Regarding claim 8, claim 2 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to read data from the plurality of memory cells in the suspend state.
Regarding claim 9, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein the fourth voltage is larger than the first voltage.
Regarding claim 12, claim 1 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to perform the second verify operation for the plurality of memory cells to check a state of the plurality of memory cells based on performing the first program loop of the program operation on the plurality of memory cells.
Regarding claim 13, claim 1 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to perform the first and second verify operation for the plurality of memory cells between the first program loop and the second program loop.
Regarding claim 14, claim 1 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to perform the second verify operation for the plurality of memory cells independent of the second program loop.
Regarding claim 15, claim 2 of the patent recites the non-volatile memory device of claim 11, wherein the control circuit is further configured to read data from the plurality of memory cells in the suspend state.
Regarding claim 16, claim 1 of the patent recites the non-volatile memory device of claim 11, wherein the fourth voltage is larger than the first voltage.
Regarding claim 19, claim 1 of the patent recites the memory system of claim 18, wherein the memory controller is configured to transmit a resume command the non-volatile memory device, and the non-volatile memory device is further configured to perform the second verify operation for the plurality of memory cells in response to receiving the resume command.
Regarding claim 20, claim 1 of the patent recites the memory system of claim 18, wherein the non-volatile memory device is further configured to read data from the plurality of memory cells in the suspend state.
Regarding claims 10, 17 and 21, it would have been obvious to one having ordinary skill in the art to recognize that the memory device and the memory system of claims 10, 18 and 21 of the instant application are used to perform the method of claim 1 of the patent.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 11,574,683. Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one having ordinary skill in the art to recognize that the memory device and the memory system are used to perform the method of claims 1 and 2 of the patent.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 6, 10 and 18 of U.S. Patent No. 11,127,465. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2-21 would have been obvious over claims 1, 2, 6, 10 and 18 of the patent.
Regarding claims 2-21, claims 1, 2, 6, 10 and 18 recites the method comprising all the seps as the functions of claims 2-21 of the instant application, for example, a plurality of memory cells and the functions of a control circuit are recited in the steps of claims 1, 2, 10 and 18 of the patent.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 10, 16 and 17 of U.S. Patent No. 11,127,465. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2-21 would have been obvious over claims 1, 2, 10, 16 and 17 of the patent.
Regarding claims 2-21, it would have been obvious to one having ordinary skill in the art to recognize that the non-volatile memory device and the memory system of claims 2-21 and the memory system and the non-volatile memory device of claims 1, 2, 10, 16 and 17 are identical in structure; therefore, the differences between two sets of claims are only functional limitations.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 21, 23 and 25 of U.S. Patent No. 10,734,078. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2-7, 9, 11-14, 16, 18 and 19 are anticipated by claims 21, 23 and 25 and claims 8, 10, 15, 17, 20 and 21 would have been obvious over claims 21, 23 and 25 of the patent.
Regarding claims 2, 11, 14, 18 and 20, claim 21 of the patent recites a non-volatile memory device comprising:
a plurality of memory cells stacked on a substrate in a vertical direction (claim 21, lines 2-4) and connected to a plurality of word lines and a plurality of bit lines; and
a control circuit (a memory controller) configured to
receive a program command (claim 21, line 6),
in response to the program command, perform a first program loop of a program operation on the plurality of memory cells by applying a first voltage to a selected word line of the plurality of word lines (claim 21, lines 11-12),
verify the plurality of memory cells by applying a second voltage to the selected word line of the plurality of word lines in response to the program command (claim 25), and
receive a suspend command,
enter a suspend state (claim 21, line 13),
receive a resume command (claim 21, line 16),
verify the plurality of memory cells by applying a third voltage to the selected word line of the plurality of word lines in response to the resume command (claim 21, lines 16-17), and
in response to the program command, perform a second program loop of the program operation on the plurality of memory cells by applying a fourth voltage to the selected word line of the plurality of word lines (claim 21, lines 18-20).
Regarding claim 3, claims 21 and 25 of the patent recite the non-volatile memory device of claim 2, wherein the control circuit is further configured to enter the suspend state after verifying the plurality of memory cells by applying the second voltage to the selected word line and before verifying the plurality of memory cells by applying the third voltage to the selected word line.
Regarding claims 4 and 12, claim 21 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the third voltage to the selected word line before performing the second program loop of the program operation on the plurality of memory cells.
Regarding claims 5 and 13, claims 21 and 25 of the patent recite the non-volatile memory device of claim 2, wherein in response to receiving the suspend command during performing the first program loop of the program operation on the plurality of memory cells, the control circuit is further configured to enter the suspend state after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line.
Regarding claim 6, claim 21 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the second voltage to the selected word line to check a state of the plurality of memory cells after performing the first program loop of the program operation on the plurality of memory cells.
Regarding claim 7, claim 25 of the patent recites the non-volatile memory device of claim 6, wherein in response to receiving the suspend command during verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells, the control circuit is further configured to enter the suspend state after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells.
Regarding claims 9 and 16, claim 23 of the patent recites the non-volatile memory device of claim 2, wherein the fourth voltage is larger than the first voltage.
Regarding claims 8, 10, 15, 17, 20 and 21. It would have been obvious to one having ordinary skill in the art to recognize that the differences between claims 8,10, 17, 20 and 21 and the claims of the patent are only functional limitations.
Regarding claim 19, claim 21 of the patent recites the memory system of claim 18, wherein the memory controller is configured to transmit a resume command the non-volatile memory device, and the non-volatile memory device is further configured to perform the second verify operation for the plurality of memory cells in response to receiving the resume command.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 10,325,658. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2-21 would have been obvious over claims 1 and 2 of the patent.
Regarding claims 2, 11, 14 and 18, claims 1 and 2 of the patent recites a non-volatile memory device comprising:
a plurality of memory cells stacked on a substrate in a vertical direction (claim 1, lines 2-4) and connected to a plurality of word lines and a plurality of bit lines; and
a control circuit (claim 1, line 9) configured to
receive a program command,
in response to the program command, perform a first program loop of a program operation on the plurality of memory cells by applying a first voltage to a selected word line of the plurality of word lines (claim 1, lines 13-14),
verify the plurality of memory cells by applying a second voltage to the selected word line of the plurality of word lines in response to the program command (claim 1, line 11), and
receive a suspend command,
enter a suspend state (claim 1, line 10),
receive a resume command,
verify the plurality of memory cells by applying a third voltage to the selected word line of the plurality of word lines in response to the resume command (claim 1, line 15), and
in response to the program command, perform a second program loop of the program operation on the plurality of memory cells by applying a fourth voltage to the selected word line of the plurality of word lines (claim 2).
Regarding claim 3, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to enter the suspend state after verifying the plurality of memory cells by applying the second voltage to the selected word line and before verifying the plurality of memory cells by applying the third voltage to the selected word line.
Regarding claims 4 and 12, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the third voltage to the selected word line before performing the second program loop of the program operation on the plurality of memory cells.
Regarding claims 5 and 13, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein in response to receiving the suspend command during performing the first program loop of the program operation on the plurality of memory cells, the control circuit is further configured to enter the suspend state after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line.
Regarding claim 6, claim 1 of the patent recites the non-volatile memory device of claim 2, wherein the control circuit is further configured to verify the plurality of memory cells by applying the second voltage to the selected word line to check a state of the plurality of memory cells after performing the first program loop of the program operation on the plurality of memory cells.
Regarding claim 7, claim 1 of the patent recites the non-volatile memory device of claim 6, wherein in response to receiving the suspend command during verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells, the control circuit is further configured to enter the suspend state after a completion of verifying the plurality of memory cells by applying the second voltage to the selected word line to check the state of the plurality of memory cells.
Regarding claim 19, claim 21 of the patent recites the memory system of claim 18, wherein the memory controller is configured to transmit a resume command the non-volatile memory device, and the non-volatile memory device is further configured to perform the second verify operation for the plurality of memory cells in response to receiving the resume command.
Regarding claims 8-10, 15-17, 20 and 21, it would have been obvious to one having ordinary skill in the art to recognize that the memory device and the memory system of claims 8-10, 15-17, 20 and 21 and the non-volatile memory device of claim 1 are identical in structure; therefore, the differences are only functional limitations.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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