DETAILED ACTION
This action is responsive to the response filed 19 Dec 2024 and the Information Disclosure Statement filed 19 Dec 2024. Claims 1-20 are pending. Claims 1, 10, and 17 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 19 Dec 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
In accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the application. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“SEMICONDUCTOR MEMORY DEVICE WITH FOUR WORD LINE DRIVES FOR TWO SETS OF WORD LINES STACKED WITH MEMORY ARRAY”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claims 2, 4 – 9, 12, 13, 15, 16, and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 17 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Simsek-Ege, F. U.S. Patent Application Publication 2024/0071467 (“Simsek”).
Regarding Claim 17, Simsek teaches:
A semiconductor memory device comprising: a first substrate; a first sub-memory cell array on the first substrate and comprising a first plurality of word lines; … a second substrate on a lower side of the first substrate; (Simsek, fig 2A, 2B, 3, “[0049] FIG. 3 illustrates an example of a material arrangement 300 that supports word line drivers for multiple-die memory devices. The material arrangement 300 illustrates an example of features that may be implemented in a semiconductor die 310, associated with a substrate 315, and a semiconductor die 340, associated with a substrate 345. [0050] The semiconductor die 310 may include one or more memory arrays 305, The memory array 305 may be associated with (e.g., include, be coupled with) word line conductors 210-a (e.g., word line conductors 210-a-l through 210-a-4 of a word line level 325), [0034] FIGS. 2A and 2B illustrate a material arrangement 200. [0035] Each memory cell 105 may include… a respective switching component 135 ( e.g., switching component 135-a, a material portion operable to couple the capacitor 130-a with a access line, such as a digit line 115).”; a device with two substrates, substrate 315 and 345; that substrate 315 comprises a memory array, word line conductors 210, and digit lines 115).
a plurality of upper metal pads in a matrix array shape on the first sub-memory cell array; one or more first metal layers electrically connecting the plurality of upper metal pads with opposite ends of each word line of the first plurality of word lines; (Simsek, fig 3, “[0051] The semiconductor die 310 also may include one or more routing layers 320 (e.g., redistribution layers), which may support conductor portions that route signals of the semiconductor die 310. For example, a routing layer 320 may include conductor portions 335, which each may be electrically coupled with a respective word line conductor 210-a (e.g., via a respective electrical contact 330 along the z-direction).”; that the 4 word lines 210-a-1/4 can drive the WL for a memory array; that the four WLs can be repeated at various locations to drive the memory cells 105).
a transistor layer on the second substrate and comprising a plurality of sub-word line drivers; (Simsek, fig 3, “[0053] The word line driver circuitry 360 may include one or more transistors formed in accordance with a transistor structure 365, each of which may be operable based at least in part on doped portions of the substrate 345. [0058] Additionally, or alternatively, one or more routing layers 350 (e.g., routing layer 350-a-4) may include conductor portions 385, which each may be electrically coupled with a respective word line driver circuit ( e.g., of the word line driver circuitry 360,”; that at least 4 word line drives can be associated with a second substrate 345 and transistor structure to drive word lines).
a plurality of lower metal pads in the matrix array shape on an upper side of the transistor layer, wherein each lower metal pad from among the plurality of lower metal pads is bonded to a corresponding upper metal pad from among the plurality of upper metal pads; and (Simsek, fig 3, “[0060] In some examples, each electrical contact 390 may extend (e.g., along the z-direction) through the substrate 345. [0062] In such examples, the respective surfaces of the semiconductor die 310 and the semiconductor die 340 may be located coincident with each other, and conductor portions 335 may be coupled with conductor portions 385 with an intervening conductor material ( e.g., respective portions of a solder material),”; that metal pads, 390 from the driver substrate and 335 from the memory cell substrate can be connected to provide connection between the two structures).
one or more second metal layers electrically connecting the plurality of lower metal pads with the transistor layer, (Simsek, fig 3, “[0060] In some examples, each electrical contact 390 may extend (e.g., along the z-direction) through the substrate 345. [0062] In such examples, the respective surfaces of the semiconductor die 310 and the semiconductor die 340 may be located coincident with each other, and conductor portions 335 may be coupled with conductor portions 385 with an intervening conductor material ( e.g., respective portions of a solder material),”; that metal pads of the transistor layer connect to the driver substrate and WLs using via 390 and 335 from the memory cell substrate can be connected to provide connection between the two structures).
wherein each first sub-word line driver from among a plurality first sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a first metal contact formed at a first end of a corresponding odd-numbered word line from among a plurality of odd-numbered word lines included in the first plurality of word lines, wherein each second sub-word line driver from among a plurality of second sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a second metal contact formed at a second end of the corresponding odd-numbered word line, wherein each third sub-word line driver from among a plurality of third sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a third metal contact formed at a first end of a corresponding even-numbered word line word line from among a plurality of even-numbered word lines included in the first plurality of word lines, and wherein each fourth sub-word line driver from among a plurality of fourth sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a fourth metal contact formed at a second end of the corresponding even-numbered word line (Simsek, fig 3, “[0060] In some examples, each electrical contact 390 may extend (e.g., along the z-direction) through the substrate 345. [0062] In such examples, the respective surfaces of the semiconductor die 310 and the semiconductor die 340 may be located coincident with each other, and conductor portions 335 may be coupled with conductor portions 385 with an intervening conductor material ( e.g., respective portions of a solder material),”; each of the four WL drivers of fig 3 are attached to the metal 390 and 334 pad to connect the transistor substrate to the memory substrate, each represented by their associated Driver to 390-335-330 to WLs 210-a-1/4).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Simsek in view of Pellizzer, et al, U.S. Patent Application Publication 2021/0295910 (“Pellizzer”).
Regarding claim 1, Simsek teaches:
A semiconductor memory device comprising: a first semiconductor structure comprising a first sub-memory cell array which comprises a first plurality of word lines, a plurality of bit lines, and a plurality of memory cells, and … (Simsek, fig 2A, 2B, 3, “[0049] FIG. 3 illustrates an example of a material arrangement 300 that supports word line drivers for multiple-die memory devices. The material arrangement 300 illustrates an example of features that may be implemented in a semiconductor die 310, associated with a substrate 315, and a semiconductor die 340, associated with a substrate 345. [0050] The semiconductor die 310 may include one or more memory arrays 305, The memory array 305 may be associated with (e.g., include, be coupled with) word line conductors 210-a (e.g., word line conductors 210-a-l through 210-a-4 of a word line level 325), [0034] FIGS. 2A and 2B illustrate a material arrangement 200. [0035] Each memory cell 105 may include… a respective switching component 135 ( e.g., switching component 135-a, a material portion operable to couple the capacitor 130-a with a access line, such as a digit line 115).”; a device with two substrates, substrate 315 and 345; that substrate 315 comprises a memory array, word line conductors 210, and digit lines 115).
a second semiconductor structure disposed under the first semiconductor structure, and comprising a plurality of sub-word line drivers, wherein the plurality of sub-word line drivers comprise: (Simsek, fig 3, “[0053] The word line driver circuitry 360 may include one or more transistors formed in accordance with a transistor structure 365, each of which may be operable based at least in part on doped portions of the substrate 345. [0058] Additionally, or alternatively, one or more routing layers 350 (e.g., routing layer 350-a-4) may include conductor portions 385, which each may be electrically coupled with a respective word line driver circuit ( e.g., of the word line driver circuitry 360,”; that at least 4 word line drives can be associated with a second substrate 345 and transistor structure to drive word lines).
a first sub-word line driver configured to supply a word line driving voltage to a first end of a first word line from among the first plurality of word lines, … a third sub-word line driver configured to supply the word line driving voltage to a first end of a second word line from among the first plurality of word lines, (Simsek, fig 3, “[0059] Each of the electrical contacts 390 may couple a respective word line conductor 210-a with a respective word line driver circuit. [0050] Although a single set of word line conductors 210-a is illustrated ( e.g., in the illustrated xz-plane ), such an arrangement may be repeated at various locations along the y-direction ( e.g., associated with a two-dimensional arrangement of word line conductors 210-a in a yz-plane) to support a three-dimensional array of memory cells 105.”; that the 4 word lines 210-a-1/4 can drive the WL for a memory array; that the four WLs can be repeated at various locations to drive the memory cells 105).
a plurality of upper metal pads electrically connected to the first plurality of word lines and the plurality of bit lines; and… a plurality of lower metal pads electrically connected to the plurality of sub-word line drivers, and (Simsek, fig 3, “[0051] The semiconductor die 310 also may include one or more routing layers 320 (e.g., redistribution layers), which may support conductor portions that route signals of the semiconductor die 310. For example, a routing layer 320 may include conductor portions 335, which each may be electrically coupled with a respective word line conductor 210-a (e.g., via a respective electrical contact 330 along the z-direction).”; that the 4 word lines 210-a-1/4 can drive the WL for a memory array; that the four WLs can be repeated at various locations to drive the memory cells 105).
wherein each upper metal pad from among the plurality of upper metal pads is bonded to a corresponding lower metal pad from among the plurality of lower metal pads in a one-to-one correspondence. (Simsek, fig 3, “[0060] In some examples, each electrical contact 390 may extend (e.g., along the z-direction) through the substrate 345. [0062] In such examples, the respective surfaces of the semiconductor die 310 and the semiconductor die 340 may be located coincident with each other, and conductor portions 335 may be coupled with conductor portions 385 with an intervening conductor material ( e.g., respective portions of a solder material),”; that metal pads, 390 from the driver substrate and 335 from the memory cell substrate can be connected to provide connection between the two structures).
Simsek does not explicitly teach … a second sub-word line driver configured to supply the word line driving voltage to a second end of the first word line, … a fourth sub-word line driver configured to supply the word line driving voltage to a second end of the second word line, and.
Pellizzer teaches … a second sub-word line driver configured to supply the word line driving voltage to a second end of the first word line, … a fourth sub-word line driver configured to supply the word line driving voltage to a second end of the second word line, and (Pellizzer, fig 1, “[0025] Similarly, the wordline decoders 108 may also be arranged into groups of wordline decoders 108, such as a first group of wordline decoders 118 and/or a second group of wordline decoders 120. Decoders may be used in combination with each other to drive the memory cells 102 (e.g., such as in pairs and/or pairs of pairs on either side of the wordlines 106 and/or bitlines 104). For example, bitline decoder 110-4 may operate in conjunction with bitline decoder 110′-4 and/or with wordline decoders 108-0, 108′-0 to select the memory cell 102A. As may be appreciated herein, decoder circuitry on either ends of the wordlines 106 and/or bitlines 104 may be different.”; two wordline decoders 108 and 108’ can be used to drive a longer word line to reduce the RC effects of using a single WL driver).
In view of the teachings of Pellizzer it would have been obvious for a person of ordinary skill in the art to apply the teachings of Pellizzer to Simsek before the effective filing date of the claimed invention in order to teach memory cell construction. The teachings of Pellizzer, in the same or in a similar field of endeavor with Simsek, can combine Pellizzer’s dual word line driver on each word line with Simsek’s single word line driver per word line. The use of two drivers, which can be located on the same plane or beneath the plane of memory cells merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 10, Simsek teaches:
A semiconductor memory device comprising: a memory cell array structure on a first substrate and comprising a plurality of sub-memory cell arrays which comprise a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a core-peripheral circuit structure on a second substrate under the first substrate, (Simsek, fig 2A, 2B, 3, “[0049] FIG. 3 illustrates an example of a material arrangement 300 that supports word line drivers for multiple-die memory devices. The material arrangement 300 illustrates an example of features that may be implemented in a semiconductor die 310, associated with a substrate 315, and a semiconductor die 340, associated with a substrate 345. [0050] The semiconductor die 310 may include one or more memory arrays 305, The memory array 305 may be associated with (e.g., include, be coupled with) word line conductors 210-a (e.g., word line conductors 210-a-l through 210-a-4 of a word line level 325), [0034] FIGS. 2A and 2B illustrate a material arrangement 200. [0035] Each memory cell 105 may include… a respective switching component 135 ( e.g., switching component 135-a, a material portion operable to couple the capacitor 130-a with a access line, such as a digit line 115).”; a device with two substrates, substrate 315 and 345; that substrate 315 comprises a memory array, word line conductors 210, and digit lines 115).
wherein the core-peripheral circuit structure comprises: a first sub-word line driver block configured to (Simsek, fig 3, “[0053] The word line driver circuitry 360 may include one or more transistors formed in accordance with a transistor structure 365, each of which may be operable based at least in part on doped portions of the substrate 345. [0058] Additionally, or alternatively, one or more routing layers 350 (e.g., routing layer 350-a-4) may include conductor portions 385, which each may be electrically coupled with a respective word line driver circuit ( e.g., of the word line driver circuitry 360,”; that at least 4 word line drives can be associated with a second substrate 345 and transistor structure to drive word lines).
supply a word line driving voltage to first ends of first odd-numbered word lines from among a first plurality of word lines in a first sub-memory cell array from among the plurality of sub-memory cell arrays, … a third sub-word line driver block configured to supply the word line driving voltage to first ends of first even-numbered word lines from among the first plurality of word lines, and (Simsek, fig 3, “[0059] Each of the electrical contacts 390 may couple a respective word line conductor 210-a with a respective word line driver circuit. [0050] Although a single set of word line conductors 210-a is illustrated ( e.g., in the illustrated xz-plane ), such an arrangement may be repeated at various locations along the y-direction ( e.g., associated with a two-dimensional arrangement of word line conductors 210-a in a yz-plane) to support a three-dimensional array of memory cells 105.”; that the 4 word lines 210-a-1/4 can drive the WL for a memory array; that the four WLs can be repeated at various locations to drive the memory cells 105; that the WL drivers drive different sets of WLs (i.e. drive even-numbered and odd-numbered WLs)).
a plurality of metal pad junctions electrically connecting the memory cell array structure with the core-peripheral circuit structure. (Simsek, fig 3, “[0051] The semiconductor die 310 also may include one or more routing layers 320 (e.g., redistribution layers), which may support conductor portions that route signals of the semiconductor die 310. For example, a routing layer 320 may include conductor portions 335, which each may be electrically coupled with a respective word line conductor 210-a (e.g., via a respective electrical contact 330 along the z-direction).”; that the 4 word lines 210-a-1/4 can drive the WL for a memory array; that the four WLs can be repeated at various locations to drive the memory cells 105).
Simsek does not explicitly teach … a second sub-word line driver block configured to supply the word line driving voltage to second ends of the first odd-numbered word lines, … a fourth sub-word line driver block configured to supply the word line driving voltage to second ends of the first even-numbered word lines; and.
Pellizzer teaches … a second sub-word line driver block configured to supply the word line driving voltage to second ends of the first odd-numbered word lines, … a fourth sub-word line driver block configured to supply the word line driving voltage to second ends of the first even-numbered word lines; and (Pellizzer, fig 1, “[0025] Similarly, the wordline decoders 108 may also be arranged into groups of wordline decoders 108, such as a first group of wordline decoders 118 and/or a second group of wordline decoders 120. Decoders may be used in combination with each other to drive the memory cells 102 (e.g., such as in pairs and/or pairs of pairs on either side of the wordlines 106 and/or bitlines 104). For example, bitline decoder 110-4 may operate in conjunction with bitline decoder 110′-4 and/or with wordline decoders 108-0, 108′-0 to select the memory cell 102A. As may be appreciated herein, decoder circuitry on either ends of the wordlines 106 and/or bitlines 104 may be different.”; two wordline decoders 108 and 108’ can be used to drive a longer word line to reduce the RC effects of using a single WL driver).
In view of the teachings of Pellizzer it would have been obvious for a person of ordinary skill in the art to apply the teachings of Pellizzer to Simsek before the effective filing date of the claimed invention in order to teach memory cell construction. The teachings of Pellizzer, in the same or in a similar field of endeavor with Simsek, can combine Pellizzer’s dual word line driver on each word line with Simsek’s single word line driver per word line. The use of two drivers, which can be located on the same plane or beneath the plane of memory cells merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Simsek, as modified by Pellizzer, in view of Li, et al, U.S. Patent Application Publication 2022/0084578 (“Li”).
Regarding claim 3, Simsek, as modified by Pellizzer, teaches the semiconductor memory device of claim 1.
Simsek, as modified by Pellizzer, does not explicitly teach wherein the first sub-word line driver and the fourth sub-word line driver are in a region under the first sub-memory cell array..
Li teaches wherein the first sub-word line driver and the fourth sub-word line driver are in a region under the first sub-memory cell array. (Li, fig 5, “[0021] Referring to FIG. 5, an integrated assembly 10 includes a base 12, a first deck 14 over the base, and a second deck 16 over the first deck. [0027] The WORDLINE DRIVER circuitry (i.e., row driver circuitry) includes regions labeled SWD-L (regions 31) and SWD-U (regions 33). The acronym SWD stands for sub-wordline-driver, [0025] In the shown embodiment, the base 12 comprises SENSE AMPLIFIER circuitry (SA), and WORDLINE DRIVER circuitry (WD).”; that multiple word line drivers, for opposite sides of the memory array can be positioned on a base-plane opposite the memory cells, that bit line sensors can also be arranged in the same plane. Note: the preposition “under” has no patentable weight other than the regions overlap their X-Y dimensions in a Z-dimension).
In view of the teachings of Li it would have been obvious for a person of ordinary skill in the art to apply the teachings of Li to Simsek before the effective filing date of the claimed invention in order to teach multi-level memory construction. The teachings of Li, in the same or in a similar field of endeavor with Simsek and Pellizzer, can combine Li’s explicit stacking of word line drivers and bit line sensing amplifiers and Simsek’s implied stacking. The explicit stacking of the two processing elements in a square overlapping memory cells merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, Simsek, as modified by Pellizzer, teaches the semiconductor memory device of claim 10.
Simsek, as modified by Pellizzer, does not explicitly teach wherein the first sub-word line driver block and the fourth sub-word line driver block are in a region under the first sub-memory cell array..
Li teaches wherein the first sub-word line driver block and the fourth sub-word line driver block are in a region under the first sub-memory cell array. (Li, fig 5, “[0021] Referring to FIG. 5, an integrated assembly 10 includes a base 12, a first deck 14 over the base, and a second deck 16 over the first deck. [0027] The WORDLINE DRIVER circuitry (i.e., row driver circuitry) includes regions labeled SWD-L (regions 31) and SWD-U (regions 33). The acronym SWD stands for sub-wordline-driver, [0025] In the shown embodiment, the base 12 comprises SENSE AMPLIFIER circuitry (SA), and WORDLINE DRIVER circuitry (WD).”; that multiple word line drivers, for opposite sides of the memory array can be positioned on a base-plane opposite the memory cells, that bit line sensors can also be arranged in the same plane. Note: the preposition “under” has no patentable weight other than the regions overlap their X-Y dimensions in a Z-dimension).
In view of the teachings of Li it would have been obvious for a person of ordinary skill in the art to apply the teachings of Li to Simsek before the effective filing date of the claimed invention in order to teach multi-level memory construction. The teachings of Li, in the same or in a similar field of endeavor with Simsek and Pellizzer, can combine Li’s explicit stacking of word line drivers and bit line sensing amplifiers and Simsek’s implied stacking. The explicit stacking of the two processing elements in a square overlapping memory cells merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Simsek, as modified by Pellizzer, in view of Lee, et al, U.S. Patent Application Publication 2022/0319575 (“Lee”).
Simsek, as modified by Pellizzer, teaches the semiconductor memory device of claim 10.
Simsek, as modified by Pellizzer, does not explicitly teach wherein the first odd-numbered word lines are arranged alternatingly with the first even-numbered word lines..
Lee teaches wherein the first odd-numbered word lines are arranged alternatingly with the first even-numbered word lines. (Lee, fig 7, 8, “[0080] FIG. 8 is a circuit diagram illustrating first and second sub-word line drivers of FIG. 7. Referring to FIGS. 1, 7, and 8, the selection circuit SC1_1 of the first sub-word line driver SWD1 may provide the first word line selection signal PXID1 to the first word line WL21 in response to a sub-word line driver enable signal NWEIB. [0085] Likewise, the non-selection circuits unSC1_2, unSC2_2, unSC1_4, and unSC2_4 corresponding to the second and fourth word lines WL22 and WL24 may be turned on in response to the second and fourth word line non-selection signals PXIB2 and PXIB4”; that even word lines can alternate with odd word lines, that the word lines can be driven by multiple WL drivers).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to Simsek before the effective filing date of the claimed invention in order to teach memory cell construction. The teachings of Lee, in the same or in a similar field of endeavor with Simsek, can combine Lee’s explicit alternating Word Lines with Drivers and Simsek’s implied alternating Word Line Drivers (“even” and “odd”) word line construction. The alternating word lines merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights