Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 8.
b. Claims 1-13 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 12/19/2024. The changes and remarks disclosed therein were considered.
Claim 4 has been amendment. Claim 13 is newly added. Therefore, claims 1-13 are pending in the application.
Drawings
3. The drawings were received on 12/19/2024 and 01/10/2025. These drawings are review and accepted by examiner.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “OF THE DICLOSURE” and “This invention provides” in page 1, lines 1-2; respectively, which are implied. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1, 3, 7-8 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0126304 A to Yoon et al. (hereafter Yoon et al).
Regarding Independent Claim 8, Yoon et al in Figures 1-8 are directly discloses a memory-paired system for multiple stacked semiconductor devices (a repair operation of a conventional memory device, Figures 1 and 3-7, paragraph 0004), comprising:
a paired unit having at least two chips (a pair of memory chips 320, 330, Fig. 3) that are identical design (the memory chip 320 and 330 receive the repair information from the repair information storage chip 310, Fig. 3, paragraph 0029);
wherein each of the at least two chips (the pair of memory chips 320 and 330) of the paired unit includes:
a memory resources module (a repair information storage chip 310, Fig. 3), configured for deploying memory resources for repair (the repair information storage chip 310 is configured to store repair information, paragraph 0028);
a paired control module (a data transmission channel 301, Fig. 3), configured for executing allocation of memory resources (the repair information storage chip 310) by:
sending a request to another one chip of the at least two chips of the paired unit (the pair of memory chips 320, 330) when memory resource of the memory resource module that the request points have been allocated (the data transmission channel 301 of the repair information storage chip 310 coupled to the pair of two chip 320 and 330, paragraph 0028); or
providing spare memory resource of the memory resource module (the repair information storage chip 310) to one chip of the paired unit based on a request from the one chip that has a failed unit existing so that the spare memory resource of the memory resource module repairs the failed unit of the one chip (for example, the memory chips 320 and 330 receive the repair information from the repair information storage chip 310 during the initial operation period of the memory system and repair their fail memory cells with redundant memory cells. Then repairing is to access a redundant memory cell to instead of a failed memory cell, when the failed memory cell is selected by an address during a read or write operation, see at least in Fig. 1 and Figs. 3-6, paragraph 0025 to paragraph 0046 and the related disclosures).
Regarding dependent Claim 12, Yoon et al in Figures 1-8 are directly discloses a memory-paired system for multiple stacked semiconductor devices (a repair operation of a conventional memory device, Figures 1 and 3-7, paragraph 0004), wherein a stacked number of the at least two chips of the paired unit (the pair of memory chips 320, 330) is even or odd (the pair of memory chips 320, 330 are even).
Regarding claims 1, 3 and 7, they encompass the same scope of invention as that of claims 8 and 12, except they draft the invention in method format instead of apparatus format. Yoon et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 1, 3 and 7, are therefore rejected in method format for the same reasons claims 8 and 12, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
6. Claims 2, 4-6, 9-11 and 13, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 9-11, the prior art fails to tech or suggest the claimed limitations, namely, the memory-paired system, wherein the paired control module comprises: a resource remapping module, configured for remapping the memory resources of the memory module based on the request from the one chip having the failed unit of the paired unit; a resource management module, configured for notifying an information regarding remapping memory resources of the resource remapping module to the one chip having the failed unit of the paired unit; wherein the resource management module of the one chip having the failed unit of the paired unit instructs a resource remapping module of it to remap memory resources of a memory resource module of it based on the information, so that the spare memory resource from the another one chip of the paired unit is allocated to the one chip having the failed unit to repair the failed unit, wherein the paired control module further comprises a paired ID module configured for storing a set of identifications that correlate the at least two chips of the paired unit, each of the at least two chips is assigned an individual identification among the identifications; and the one chip having the failed unit of the paired unit identifies the another one chip of the paired unit according to the set of the identifications.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, the repair method further comprising: remapping resources of the another one chip of the paired unit when the another one chip of the paired unit receiving the request; notifying an information of resource remapping of the another one chip of the paired unit to the one chip having the failed unit of the paired unit; remapping resources of the one chip having the failed unit of the paired unit based on the information to correspond to a resource state of the one chip having the failed unit of the paired unit receiving the spare resource from the another one chip of the paired unit.
With respected to dependent claims 4-6, the prior art fails to tech or suggest the claimed limitations, namely, the repair method further comprising: assigning an individual identification to each chip of the pair unit and correlating the pair unit to a set of the individual identifications assigned to the chips grouped in the pair unit; wherein the one chip having the failed unit of the paired unit identifies the another one chip of the paired unit according to the set of the individual identifications.
With respected to dependent claim 13, the prior art fails to tech or suggest the claimed limitations, namely, the repair method, further comprising: assigning an individual identification to each chip of the pair unit and correlating the pair unit to a set of the individual identifications assigned to the chips grouped in the pair unit; wherein the one chip having the failed unit of the paired unit identifies the another one chip of the paired unit according to the set of the individual identifications.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
D’Abreu (US. 8,947,931 B1) discloses a data storage device includes a memory die in memory module.
Kim et al (US. 2018/0158809 A1) discloses semiconductor memory device including stacked and memory module having the same.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights