DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 12/19/2024. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bonen et al. (WO 2016/048634 A1) (“Bonen”) in view of Williams et al. (US 6,584,543 B2) (“Williams”).
Claim 1: Bonen teaches (e.g. in e.g., paragraphs [0014], [0021]-[0023], [0028], and [0030]) a method, comprising:
receiving, at a first channel of a memory device, a first plurality of bits that comprises data (e.g., Bonen teaches a DQ interface (first channel) for receiving data. See p. 11, ll. 13-22; p. 12, ll. 1-15);
receiving, at a second channel of the memory device, a second plurality of bits that comprises metadata and first error control information (e.g., Bonen teaches a DM interface (second/sideband channel) for receiving metadata and error control information. See p. 1, ll. 13-22; p. 11, ll. 13-22; p. 12, ll. 1-15).
Not explicitly taught by Bonen is:
communicating, via a multiplexor, the first error control information or second error control information to a first plurality of memory cells of a first memory array of the memory device, the second error control information associated with the data; and
communicating the data to a second plurality of memory cells of a second memory array of the memory device based at least in part on communicating the first error control information or the second error control information to the first plurality of memory cells.
However, as per item (a), Williams teaches a primary multiplexer (54) that routes ECC bits to high-order banks (first plurality). See col. 7, ll. 54-67; col. 8, ll. 1-15. And as per item (b), Bonen teaches storing data in data storage (222) and ECC in ECC storage (224). And Williams teaches that data is stored in low-order banks (44) based on the multiplexer’s routing of ECC to high-order banks (46). See col. 7, ll. 54-67; col. 8, ll. 1-15.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Bonen and Williams. Bonen provides the framework for a dual-channel (data and sideband) interface that carries metadata and error control information. Williams provides the internal memory architecture and multiplexer-based routing that allows the error control information received over the sideband channel to be selectively stored in a dedicated ECC memory array, while data is stored in a separate data array. The combination is a straightforward integration of known components: a sideband interface (Bonen) with a reconfigurable memory array having a multiplexer for ECC/data routing (Williams). This yields predictable results, which is efficient handling of metadata and error control information without undue experimentation. A person of ordinary skill would have been motivated to combine these references to improve flexibility and storage efficiency in memory systems.
Claim 2: Bonen and Williams teach the method of claim 1, further comprising: receiving a read command associated with the data; communicating the data to the first channel based at least in part on receiving the read command; and communicating the first error control information or the second error control information to the second channel based at least in part on receiving the read command (e.g., Bonen describes read operations where data and metadata are sent to the memory controller. See paragraphs [0028]-[0030]. Williams describes read operations where data and ECC bits are retrieved. See col. 8, ll. 64-67; col. 9, ll. 1-5).
Claim 3: Bonen and Williams teach the method of claim 2, but fail to further teach: accessing the data from the second plurality of memory cells, wherein communicating the data to the first channel is based at least in part on accessing the data from the second plurality of memory cells; and accessing the first error control information or the second error control information from the first plurality of memory cells, wherein communicating the first error control information or the second error control information to the second channel and communicating the data to the first channel occur during an overlapping duration. However, Bonen teaches accessing stored data and associated metadata from memory storage locations during read operations. Bonen further teaches separate data and metadata interfaces, permitting concurrent communication of data and metadata. Therefore, it would have been obvious that communications through separate interfaces occur during overlapping time periods to improve memory throughput and efficiency.
Claim 4: Bonen and Williams teach the method of claim 1, further comprising: receiving a write command associated with the first plurality of bits and the second plurality of bits, wherein communicating the first error control information or the second error control information is based at least in part on receiving the write command (e.g., Bonen describes write operations where data and metadata are received. See paragraphs [0023]-[0030]. Williams describes write operations where ECC bits are stored based on a write command. See col. 8, ll. 64-67; col. 9, ll. 1-5).
Claim 5: Bonen and Williams teach the method of claim 1, further comprising: generating, by an error control circuit, the second error control information based at least in part on the first plurality of bits, wherein communicating the first error control information or the second error control information is based at least in part on generating the second error control information (e.g., Bonen teaches the memory controller can generate error correction information. See paragraphs [0021]-[0024]. Williams teaches an error correction circuit (56) that generates ECC bits. See col. 8, ll. 64-67; col. 9, ll. 1-5).
Claim 6: Bonen and Williams teach the method of claim 1, wherein the first channel is associated with a data channel of the memory device, and wherein the second channel is associated with a sideband channel of the memory device (e.g., Bonen explicitly teaches DQ as data channel and DM as sideband channel. See p. 11, ll. 13-22; p. 12, ll. 1-15).
Claim 7: Bonen and Williams teach the method of claim 1, wherein the first error control information or the second error control information comprises error correction code information, error detection code information, single error correction double error detection information, or any combination thereof (e.g., Bonen explicitly lists ECC, error detection, and SECDED as types of metadata. See p. 3, ll. 13-22; p. 4, ll. 1-10).
Claims 8-14 are directed to a memory system corresponding to the method of claims 1-7. Bonen teaches the claimed first channel, second channel, memory arrays, ECC circuitry, and processing circuitry. Williams teaches the claimed multiplexor architecture used for routing ECC information. Therefore claims 8-14 would have been obvious for substantially the same reasons set forth with respect to claims 1-7.
Claims 15-20 are directed to a non-transitory computer-readable medium storing instructions executable to perform operations corresponding to claims 1-7. Because the underlying operations are taught or suggested by Bonen in view of Williams, it would have been obvious to store instructions implementing such operations on a non-transitory computer-readable medium. Therefore claims 15-20 would have been obvious.
Conclusion
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 6/18/2026
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