DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 4: it appears that “a coarse programming state” in line(s) 1-2 was meant to be -- the coarse programming state --.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Im (2015/0357043) in view of Yamada et al. (US 2021/0082510 -hereinafter Yamada).
Regarding claim 1, Im discloses a system comprising:
a memory device (120; fig. 1-3); and
a processing device (110; fig. 1-2), operatively coupled with the memory device, to perform operations [0055+]] comprising:
determining a difference (i.e. elapsed time [0096]) between a recorded time stamp (time stamp t0, when evaluation data is programmed; fig. 13) for a set of memory cells (any set of 1st/2nd/3rd/4th memory cells; fig. 13) and a current time stamp (any of time stamp t1, t2, t3, respectively; fig. 13);
determining (i.e. evaluating), based on the difference between the recorded time stamp and the current time stamp (i.e. based on the elapsed time), that the set of memory cells is in a programming state (Yes at S210, in which the memory cells are considered in a programming state by evaluation data DATA_e programmed into the memory cells; fig. 12 [0050, 0069]); and
performing, using a programming state verify level associated with the set of memory cells (Vvfy1; fig. 8), a programming operation (circle 1, 3, 6…; fig. 13) on the set of memory cells set of 1st/2nd/3rd/4th memory cells, respectively; fig. 13).
Im does not expressly disclose coarse programming state; and reduced programming state verify level.
Yamada discloses disclose coarse programming state (a verification operation determines a programming state of memory cells [0060], i.e. foggy programming state; fig. 9A [0105]); and reduced programming state verify level (i.e. responsive to the verification operation determining that the second set of memory cells completed the foggy programming state, a programming state verify level is reduced from CV-GV to AV, BV...; fig. 9A-9B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 2, Im discloses the system of claim 1, wherein the set of memory cells is comprised by an open translation (TU) unit of memory cells (a unit including physical word lines with programmed memory cells and memory cells open for programming; fig. 13).
Regarding claim 3, Im discloses the system of claim 1, wherein the set of memory cells comprises a most recently programmed set of memory cells (fig. 13).
Regarding claim 4, Im discloses the system of claim 1, wherein determining that the set of memory cells is in a programming state is further based on current temperature for the set of memory cells [0090].
Yamada discloses coarse programming state (fig. 9A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 5, Yamada discloses the system of claim 1, wherein the programming operation is performed using a reduced programming state gate step size (fig. 9A-9B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 6, Im discloses the system of claim 1, wherein the operations further comprise: identifying a threshold voltage distribution shift for a first wordline (WL) [0084] based on a read operation to be performed on the set of memory cells [0135+], wherein the set of memory cells is addressable by the first WL [0064].
Regarding claim 7, Yamada discloses the system of claim 1, wherein the processing device is to perform operations further comprising: identifying a threshold voltage distribution shift [0096] for a first wordline (WL) based on a trim operation (i.e. trimming of the threshold voltage distribution from the foggy to fine threshold voltage; fig. 8A-8D) to be performed on the set of memory cells, wherein the set of memory cells is addressable by the first WL (MCG of WLO; fig. 11).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 8, Im discloses the system of claim 1, wherein the processing device is to perform operations further comprising: performing a programming operation on the set of memory cells (fig. 13), wherein first set of memory cells is addressable by a first wordline (WL) [0064].
Regarding claim 9, Im discloses the method comprising:
determining a difference (i.e. elapsed time [0096]) between a recorded time stamp (time stamp t0, when evaluation data is programmed; fig. 13) for a set of memory cells (any set of 1st/2nd/3rd/4th memory cells; fig. 13) and a current time stamp for the set of memory cells (any of time stamp t1, t2, t3, respectively; fig. 13);
determining (i.e. evaluating), based on the difference between the recorded time stamp and the current time stamp (i.e. based on the elapsed time), that the set of memory cells is in a programming state (Yes at S210, in which the memory cells are considered in a programming state by evaluation data DATA_e programmed into the memory cells; fig. 12 [0050, 0069]); and
performing, using a programming state verify level associated with the set of memory cells (Vvfy1; fig. 8), a programming operation (circle 1, 3, 6…; fig. 13) on the set of memory cells set of 1st/2nd/3rd/4th memory cells, respectively; fig. 13).
Im does not expressly disclose coarse programming state; and reduced programming state verify level.
Yamada discloses disclose coarse programming state (a verification operation determines a programming state of memory cells [0060], i.e. foggy programming state; fig. 9A [0105]); and reduced programming state verify level (i.e. responsive to the verification operation determining that the second set of memory cells completed the foggy programming state, a programming state verify level is reduced from CV-GV to AV, BV...; fig. 9A-9B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 10, Im discloses the method of claim 9, wherein the set of memory cells is comprised by an open translation (TU) unit of memory cells (a unit including physical word lines with programmed memory cells and memory cells open for programming; fig. 13).
Regarding claim 11, Im discloses the method of claim 9, wherein the set of memory cells comprises a most recently programmed set of memory cells (fig. 13).
Regarding claim 12, Im discloses the method of claim 9, wherein determining that the set of memory cells is in the programming state is further based on current temperature for the set of memory cells [0090].
Yamada discloses coarse programming state (fig. 9A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 13, Yamada discloses the method of claim 9, wherein performing the programming operation further uses a reduced programming state gate step size (fig. 9A-9B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 14, Im discloses the method of claim 9, the method further comprising:
identifying a threshold voltage distribution shift for a first wordline (WL) [0084] based on a read operation to be performed on the set of memory cells [0135+], wherein the set of memory cells is addressable by the first WL [0064].
Regarding claim 15, Yamada discloses the method of claim 9, the method further comprising:
identifying a threshold voltage distribution shift [0096] for a first wordline (WL) based on a trim operation (i.e. trimming of the threshold voltage distribution from the foggy to fine threshold voltage; fig. 8A-8D) to be performed on the set of memory cells, wherein the set of memory cells is addressable by the first WL (MCG of WLO; fig. 11).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 16, Im discloses a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
determining a difference (i.e. elapsed time [0096]) between a recorded time stamp (time stamp t0, when evaluation data is programmed; fig. 13) for a set of memory cells (any set of 1st/2nd/3rd/4th memory cells; fig. 13) and a current time stamp for the set of memory cells (any of time stamp t1, t2, t3, respectively; fig. 13);
determining (i.e. evaluating), based on the difference between the recorded time stamp and the current time stamp (i.e. based on the elapsed time), that the set of memory cells is in a programming state (Yes at S210, in which the memory cells are considered in a programming state by evaluation data DATA_e programmed into the memory cells; fig. 12 [0050, 0069]); and
performing, using a programming state verify level associated with the set of memory cells (Vvfy1; fig. 8), a programming operation (circle 1, 3, 6…; fig. 13) on the set of memory cells set of 1st/2nd/3rd/4th memory cells, respectively; fig. 13).
Im does not expressly disclose coarse programming state; and reduced programming state verify level.
Yamada discloses disclose coarse programming state (a verification operation determines a programming state of memory cells [0060], i.e. foggy programming state; fig. 9A [0105]); and reduced programming state verify level (i.e. responsive to the verification operation determining that the second set of memory cells completed the foggy programming state, a programming state verify level is reduced from CV-GV to AV, BV...; fig. 9A-9B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 17, Im discloses the non-transitory computer-readable storage medium of claim 16, wherein the set of memory cells is comprised by an open translation (TU) unit of memory cells (a unit including physical word lines with programmed memory cells and memory cells open for programming; fig. 13).
Regarding claim 18, Im discloses the non-transitory computer-readable storage medium of claim 16, wherein the set of memory cells comprises a most recently programmed set of memory cells (fig. 13.
Regarding claim 19, Im discloses the non-transitory computer-readable storage medium of claim 16, wherein determining that the set of memory cells is in a programming state is further based on current temperature for the set of memory cells [0090].
Yamada discloses coarse programming state (fig. 9A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Regarding claim 20, Yamada discloses the non-transitory computer-readable storage medium of claim 16, wherein performing the programming operation further uses a reduced programming state gate step size (fig. 9A-9B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Im is modifiable as taught by Yamada for the purpose of improving write operations with different program techniques, which facilitates data accessing schemes by reducing disturbances to improve the overall integrity of data storage [0077 of Yamada].
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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