Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 19, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed December 19, 2024 through May 8, 2026 have been
considered.
Claim Objections
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 6 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
1. A memory device comprising: a memory array comprising a plurality of rows, wherein each row of the plurality of rows comprises a plurality of count value memory cells configured to store a count value representing a number of activations of a corresponding one of the plurality of rows; and an alert pin configured to provide an active alert signal when a number of activations of a row of the plurality of rows reaches a threshold value.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
2. The memory device of claim 1, further comprising a mode register configured to store the threshold value.
See claim 1 and remarks below.
3. The memory device of claim 1, further comprising memory cells configured to store information to detect errors in the count value.
6. The apparatus of claim 1, wherein the plurality of count value memory cells are further configured to store error correction code information associated with the plurality of values.
4. The memory device of claim 1, wherein the memory device is configured to perform targeted refreshes.
2. The apparatus of claim 1, wherein the refresh control circuit is further configured to activate a busy signal provided to an external pin when performing the targeted refresh operation.
5. The memory device of claim 4, wherein the targeted refreshes are performed on rows physically adjacent to the row.
See claim 1 and remarks below.
6. The memory device of claim 1, wherein the memory device is configured to perform refreshes on the plurality of rows, wherein the targeted refreshes refresh the count value memory cells of the plurality of rows.
See claim 1 and remarks below.
As can be seen from the above table, both, claim 1 of the application and claim 1 of the patent, are drawn to memory apparatuses, differing only in preamble terminology (it is noted that "Rows" and "word lines" are used interchangeably in the memory arts to denote the same structural feature across a memory array). Both employ count value memory cells assigned to each respective line/row to track and store the number of times that specific row or word line is activated. Both describe the core function of evaluating a tracked activation count against a preset threshold and generating a signal when the limit is reached. The alert pin in claim 1 of the application is merely an external output mechanism for the internal trigger signal generated by the count control circuit in claim 1 of the patent. Claim 1 of the application adds nothing more, to claim 1 of the patent, than a physical pin (an alert pin) to route the internal trigger signal out of the device. Providing a pin to output an internal status/trigger signal is a standard, well-known design choice in electrical and semiconductor engineering. It does not create a novel or non-obvious operational feature. Additionally, all substantive limitations of claim 1 of the application are fully disclosed and structurally accounted for in claim 1 of the patent. Because claim 1 of the application merely defines an output pin for a condition that claim 1 of the patent’s circuitry already evaluates and signals internally, the claims of claim 1 of the application are at best a mere obvious variation of claim 1 of the patent. Thus, coverage has already been given to the earlier filed patent application.
With respect to claim 2, claim 2 introduces a "mode register" to store the threshold value. A person having ordinary skill in the art would find it obvious to store this programmable threshold variable in a conventional mode register, which is specifically designed to store such parameters. Claim 1 of the patent already dictates the need for comparing against a "threshold value". Implementing that threshold via a programmable register is considered a basic, predictable variation that yields no unexpected results. Thus, coverage has already been given to the earlier filed patent application.
With respect to claim 5, the term "targeted refresh operation" in claim 1 of the patent inherently implies a refresh operation designed to mitigate Row Hammer effects (preventing data corruption in heavily accessed rows). In standard memory architectures, targeted refresh operations are directed at the "aggressor" row's immediately adjacent, physically victimized rows. While claim 1 of the patent broadly recites performing a "targeted refresh," using claim 5 of the application merely details the standard, well-known industry method of executing that targeted refresh. Therefore, this additional limitation in claim 5 of the application is an obvious variation that would not overcome a rejection over claim 1 of the patent. Thus, coverage has already been given to the earlier filed patent application.
With respect to claim 6, claim 1 of the patent explicitly includes a "refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received." In claim 1 of the patent, performing a targeted refresh necessarily accesses and acts upon the target row. Memory devices refresh the data and state within the memory cells (which includes the count value memory cells) of that row during these access operations. Therefore, the targeted refresh operation inherently refreshes the count value memory cells as described in claim 6 of the application, making this additional limitation an obvious design choice, inherent operation, or well-known physical property of performing a refresh to the targeted row. Thus, coverage has already been given to the earlier filed patent application.
Claims 7-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 9 and 10 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
7. A method comprising: counting a number of activations of a row; and storing the number of activations in a plurality of count value memory cells; activating an alert signal when the number of activations reaches a threshold value.
7. A method comprising: storing a plurality of values each representing a different one of a number of activations of a word line in a plurality of count value memory cells of the word line; comparing a value of the plurality of values to a threshold value with a count control circuit; and activating a trigger signal when the value is equal to or greater than the threshold value; and updating the value when the value is below the threshold value.
8. The method of claim 7, further comprising storing the threshold value in a mode register.
See claim 7 and remarks below.
9. The method of claim 7, further comprising receiving the threshold value from a controller.
See claim 7 and remarks below.
10. The method of claim 7, further comprising performing a targeted refresh operation.
10. The method of claim 9, further comprising performing a targeted refresh operation.
11. The method of claim 10, wherein the targeted refresh operation is performed responsive to the number of activations reaching the threshold value.
See claim 7 and remarks below.
12. The method of claim 10, wherein the targeted refreshes are performed on rows physically adjacent to the row.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
As can be seen from the above table, both, claim 7 of the application and claim 7 of the patent,
have elements cover maintaining activation tracking metrics within dedicated memory regions.
Both teach logic checking to see if a specific row has been accessed too frequently. Both dictate generating an operational response (e.g., triggering a targeted neighbor refresh) once a threshold is met. Both require updating the database/counter incrementally as long as the threshold hasn't been met. Therefore, coverage has already been given to the earlier filed patent application.
With respect to claim 8, claim 7 of the patent teaches setting or utilizing a threshold value for memory maintenance (like refresh tracking), adapting that architecture to save the threshold value inside an on-chip mode register represents nothing more than a predictable use of known components according to their established functions. A person of ordinary skill in the art would naturally choose a mode register to store such configuration variables to ensure the memory controller can dynamically alter or read the threshold during boot-up or runtime calibration. Therefore, adding a mode register limitation fails to provide a patentably distinct, non-obvious over claim 7 of the patent. Thus, coverage has been given to the earlier filed patent application.
With respect to claim 9, in standard computer architecture, registers containing static or dynamic risk mitigation criteria are inherently programmatically distributed or refreshed by the system's central memory controller. It would be entirely obvious to a person having ordinary skill in the art to implement the step of claim 9 of the application because a controller is a universal mechanism for sending operating thresholds to localized memory control circuits. Modifying claim 7 of the patent to define the origin of the threshold value as "the controller" relies on standard, off-the-shelf design choices and yields a completely predictable result. Therefore, coverage have already been given to the earlier filed patent application.
With respect to claim 11, claim 7 of the patent explicitly states that it is "activating a trigger signal when the value is equal to or greater than the threshold value". In semiconductor memory architecture (DRAM), a trigger signal tied directly to a word line activation count threshold inherently performs or schedules a targeted refresh operation to prevent data corruption on victim rows. Because the trigger signal of claim 7 of the patent is structurally and logically responsive to the activations reaching the threshold, executing a refresh "responsive to" that trigger is either explicitly disclosed or would be entirely obvious to a person having ordinary skill in the art. Therefore, claim 11 of the application lacks patentable novelty over claim 7 of the patent. Therefore, coverage has been given to the earlier filed patent application.
With respect to claim 12, the term "targeted refresh operation" in claim 1 of the patent inherently implies a refresh operation designed to mitigate Row Hammer effects (preventing data corruption in heavily accessed rows). In standard memory architectures, targeted refresh operations are directed at the "aggressor" row's immediately adjacent, physically victimized rows. While claim 1 of the patent broadly recites performing a "targeted refresh," using claim 5 of the application merely details the standard, well-known industry method of executing that targeted refresh. Therefore, this additional limitation in claim 5 of the application is an obvious variation that would not overcome a rejection over claim 1 of the patent. Thus, coverage has already been given to the earlier filed patent application.
Claims 14-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
14. A method comprising: provide a row activation command for a row from a controller to a memory device; and receive an active alert signal from the memory device, wherein the active alert signal indicates a number of activations of the row has reached a threshold value.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
15. The method of claim 14, further comprising providing the threshold value to the memory device.
See claim 1 and the remarks below.
16. The method of claim 14, further comprising providing a precharge command a time after providing the row activation command.
4. The apparatus of claim 1, wherein the count control circuit is further configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received.
17. The method of claim 15, further comprising providing a refresh command to the memory device.
See claim 1 and remarks below.
As can be seen from the above table, claim 14 of the application recites, "provide a row
activation command for a row from a controller to a memory device". Claim 1 of the patent discloses a "count control circuit configured to receive ... when the word line [row] is activated". In semiconductor memory architectures, a row is selected and activated by providing an activation command from a controller (e.g., memory controller) to the memory device. Because claim 1 of the patent includes a count control circuit that evaluates a word line when it is activated, claim 1 of the patent inherently anticipates the step of providing an activation command to initiate this process.
Claim 14 of the application recites, "receive an active alert signal from the memory device". Claim 1 of the patent features a "count control circuit configured to ... compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value". An active alert signal in, claim 14 of the application, is a signal sent upon reaching a row activation threshold. Similarly, the "trigger signal" in claim 1 of the patent is activated (and subsequently sent or received internally in the apparatus) when the threshold value is reached. This satisfies the alert signal functionality.
Claim 14 of the application recites, "wherein the active alert signal indicates a number of
activations of the row has reached a threshold value.” Claim 1 of the patent includes "a plurality of count value memory cells configured to store a plurality of values each representing a number of activations ... compare the value to a threshold value and activate a trigger signal when ... equal to or greater than the threshold value". Both claims rely on the identical logical trigger condition: tracking row activations and determining when they meet or exceed a specific threshold limit. Therefore, claim 1 of the patent describes exactly how this alert signal state is generated and indicated. Because claim 1 of the patent describes all the functional limitations of claim 14 of the application. While claim 14 of the application is framed as a method (what the system does) and claim 1 of the patent as an apparatus (the physical device), apparatus claims that include "configured to" language are typically treated as structural equivalents to corresponding methods of operation. Claim 1 of the patent explicitly covers the controller, memory device actions, and row activation monitoring necessary to perform claim 14 of the application. Therefore, coverage has been given to the earlier filed patent application.
With respect to claim 15, claim 15 of the application recites, “"providing the threshold value to the memory device". Claim 1 of the patent’s count control circuit is configured to "compare the value to a threshold value." In order for the circuit to perform this comparison, the threshold value must inherently be provided to or stored within the memory device itself. Claim 1 of the patent dictates that the hardware apparatus must store and evaluate a "threshold value." Without the ability to receive, program, or access this threshold value, claim 1 of the patent's claim limitation requiring a circuit to "compare the value to a threshold value" could not function. Therefore, the provision of the threshold value is an inherent structural and operational requirement of the claim 1 of the patent apparatus, making claim 15 of the application obvious or anticipated in light of claim 1 of the patent.
With respect to claim 16, claim 16 of the application recites, “Providing a precharge command a time after providing the row activation command.” The combination of claims 1 and 4 of the include "a count control circuit configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received." In standard memory operations (e.g., DRAM), memory controllers must issue a precharge command after activating a row. The combination of claims 1 and 4 inherently require a precharge command to execute its own "update" step. Therefore, providing a precharge command after an activation command is a standard, required mechanism in the memory architecture described in the combination, making it proper to reject claim 16 of the application as it lacks a novel or unexpected distinction over the combination of the claims of the patent's standard operational flow. Therefore, coverage has already been given to the earlier filed patent application.
With respect to claim 17, claim 17 of the application recites, “providing a refresh command to the memory device”. Claim 1 of the patent recites, “"...activate a trigger signal when the value is equal to or greater than the threshold value... latch a current row address and perform a targeted refresh operation..." While claim 1 of the patent recites generating an internal "trigger signal" to perform a targeted refresh, providing a refresh command (which triggers internal refresh circuitry) is structurally and functionally synonymous. Therefore, it is proper to reject claim 17 of the application because the hardware components (count control circuit and refresh control circuit) of claim 1 of the patent natively execute a targeted refresh operation based on their internal metrics. An apparatus claim inherently encompasses the method of using the apparatus. When a device like claim 1 of the patent includes control circuitry configured to perform a targeted refresh operation, a method claim reciting "providing a refresh command to the memory device" covers the exact physical operation that claim 1 of the patent performs. Thus, coverage has already been given to the earlier filed patent application.
Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
18. An apparatus comprising: a memory controller configured to: receive an active alert signal from a memory device, wherein the active alert signal indicates a number of activations of a row has reached a threshold value; and provide the threshold value to the memory device.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
19. The apparatus of claim 18, wherein the controller is further configured to provide a row activation command and a precharge command to the memory device.
4. The apparatus of claim 1, wherein the count control circuit is further configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received.
20. The apparatus of claim 18, wherein the controller is further configured to provide a refresh command to the memory device.
See claim 1 and remarks below.
Claim 18 of the application recites, “An apparatus comprising: a memory controller configured to..." Claim 1 of the patent outlines an apparatus (memory system) with corresponding control circuits (e.g., count control circuit, refresh control circuit) that operate as a memory controller. Claim 18 of the application recites, “"...receive an active alert signal from a memory device..." Claim 1 of the patent discloses a "trigger signal" (active alert) activated by the count control circuit when the row's activation value reaches or exceeds the threshold. Claim 18 of the application recites, "...wherein the active alert signal indicates a number of activations of a row has reached a threshold value..." Claim 1 of the patent's trigger signal is activated when a counted "number of activations of a corresponding one of the plurality of word lines" equals or exceeds a "threshold value." Claim 18 of the application recites, "...and provide the threshold value to the memory device." Claim 1 of patent's count control circuit must have access to or store this threshold value to perform the comparison operation ("compare the value to a threshold value"), inherently providing/applying it. Claim 18 of the application is an apparatus claim reciting functional capabilities that map perfectly onto the built-in control circuits (count control/refresh control) of Claim 1 of the patent. Because the specific operations (counting activations, comparing to a threshold, and triggering an alert) are identically disclosed in Claim 1 of the patent, the limitations of claim 18 of the application do not present a distinct invention, rendering it unpatentable over claim 1 of the patent. Coverage has already been given to the earlier filed patent application.
With respect to claim 19, claim 19 of the application recites, “Providing a precharge command a time after providing the row activation command.” The combination of claims 1 and 4 of the include "a count control circuit configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received." In standard memory operations (e.g., DRAM), memory controllers must issue a precharge command after activating a row. The combination of claims 1 and 4 inherently require a precharge command to execute its own "update" step. Therefore, providing a precharge command after an activation command is a standard, required mechanism in the memory architecture described in the combination, making it proper to reject claim 19 of the application as it lacks a novel or unexpected distinction over the combination of the claims of the patent's standard operational flow. Therefore, coverage has already been given to the earlier filed patent application.
With respect to claim 20, claim 20 of the application recites, “providing a refresh command to the memory device”. Claim 1 of the patent recites, “"...activate a trigger signal when the value is equal to or greater than the threshold value... latch a current row address and perform a targeted refresh operation..." While claim 1 of the patent recites generating an internal "trigger signal" to perform a targeted refresh, providing a refresh command (which triggers internal refresh circuitry) is structurally and functionally synonymous. Therefore, it is proper to reject claim 20 of the application because the hardware components (count control circuit and refresh control circuit) of claim 1 of the patent natively execute a targeted refresh operation based on their internal metrics. An apparatus claim inherently encompasses the method of using the apparatus. When a device like claim 1 of the patent includes control circuitry configured to perform a targeted refresh operation, a method claim reciting "providing a refresh command to the memory device" covers the exact physical operation that claim 1 of the patent performs. Thus, coverage has already been given to the earlier filed patent application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nale [US Patent Application # 20190066808].
With respect to claim 1, Nale discloses a memory device comprising ["...The row activation count control and monitoring logic circuitry 403 reads the activation count value..." – par. 0028 (The memory device is inherently described by the structural components and monitoring circuitry.)]: a memory array comprising a plurality of rows ["...for the victim rows of the particular row that has just been activated." – par. 0028 (The reference inherently discloses a memory array because it discusses rows and victim rows that are actively activated.)], wherein each row of the plurality of rows comprises a plurality of count value memory cells configured to store a count value ["...reads the activation count value for the activated row from the corresponding buffer segments 402..." – par. 0028 (The reference explicitly discloses storing an activation count value in corresponding buffer segments (memory cells) representing the row's number of activations.)] representing a number of activations of a corresponding one of the plurality of rows ["...represents a number of activations of a corresponding one of the plurality of rows [that has just been activated]." – par. 0028 (the stored count value corresponds to the activation numbers of the specific rows.)]; and an alert pin configured to provide an active alert signal ["...the row activation count control and monitoring logic circuitry raises an alert signal 305..." – par. 0028 (The alert signal in the reference is the functional equivalent of the "alert pin" limitation, as it serves to output/indicate when protection is needed.)] when a number of activations of a row of the plurality of rows reaches a threshold value ["If the incremented count value equals (or exceeds) the threshold value, the row activation count control and monitoring logic circuitry raises an alert signal..." – par. 0028 (the raising of the alert signal is strictly tied to the condition of reaching the threshold value (e.g., P/2).)].
With respect to claim 2, Nale disclose a mode register configured to store the threshold value [The threshold value P/2 may be loaded or derived from a value (e.g., P) that is stored within the memory, e.g., within a mode register (MR) – par. 0029].
With respect to claim 3, Nale disclose memory cells configured to store information to detect errors in the count value [the storage array corresponds to the typical storage capacity of a traditional DRAM and includes: 1) storage cells for customer data; 2) error correction code (ECC) storage cells; and, 3) spare storage cells. – par. 0022].
With respect to claim 4, Nale disclose the memory device is configured to perform targeted refreshes [The reference implies performing targeted refreshes. When an alert signal is raised because a row has reached the activation threshold, protection is triggered to prevent data corruption (a process inherently carried out via targeted refreshes of the threatened/victim rows).].
Claim(s) 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nale [US Patent Application # 20190066808].
With respect to claim 7, Nale discloses a method comprising: counting a number of activations of a row ["...reads the activation count value for the activated row from the corresponding buffer segments 402..." – par. 0028 (The reference explicitly discloses storing an activation count value in corresponding buffer segments (memory cells) representing the row's number of activations.)]; and storing the number of activations in a plurality of count value memory cells ["...represents a number of activations of a corresponding one of the plurality of rows [that has just been activated]." – par. 0028 (the stored count value corresponds to the activation numbers of the specific rows.)]; activating an alert signal when the number of activations reaches a threshold value ["...the row activation count control and monitoring logic circuitry raises an alert signal 305..." – par. 0028 (The alert signal in the reference is the functional equivalent of the "alert pin" limitation, as it serves to output/indicate when protection is needed.)].
With respect to claim 8, Nale discloses storing the threshold value in a mode register [The threshold value P/2 may be loaded or derived from a value (e.g., P) that is stored within the memory, e.g., within a mode register (MR) – par. 0029].
With respect to claim 9, Nale discloses receiving the threshold value from a controller [“The row activation count control and monitoring logic circuitry 403 then compares 304 the incremented value against a threshold value” – par. 0028].
With respect to claim 10, Nale discloses performing a targeted refresh operation [“the refresh circuitry to refresh potential victim rows of the potential disturber row in response to a signal sent by the logic circuitry.” – claim 9].
Claim(s) 14, 15 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nale [US Patent Application # 20190066808].
With respect to claim 14, Nale discloses a method comprising: provide a row activation command for a row from a controller to a memory device ["...The row activation count control and monitoring logic circuitry 403 reads the activation count value..." – par. 0028 (The memory device is inherently described by the structural components and monitoring circuitry.)]; and receive an active alert signal from the memory device ["...the row activation count control and monitoring logic circuitry raises an alert signal 305..." – par. 0028 (The alert signal in the reference is the functional equivalent of the "alert pin" limitation, as it serves to output/indicate when protection is needed.)], wherein the active alert signal indicates a number of activations of the row has reached a threshold value ["If the incremented count value equals (or exceeds) the threshold value, the row activation count control and monitoring logic circuitry raises an alert signal..." – par. 0028 (the raising of the alert signal is strictly tied to the condition of reaching the threshold value (e.g., P/2).)].
With respect to claim 15, Nale discloses providing the threshold value to the memory device [The threshold value P/2 may be loaded or derived from a value (e.g., P) that is stored within the memory, - par. 0029].
With respect to claim 17, Nale discloses providing a refresh command to the memory device [each next refresh command that is received by the DRAM from the memory controller – par. 0030].
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 13: The method of claim 10, wherein the targeted refreshes are performed on rows having a different physical relationship to the row.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 9, 2026
Prosecution Insights