Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 18, 2026, claims 1-3, 6-9, 11, 13-15 and 17-20
are active in this application.
Information Disclosure Statement
The information disclosure statement filed June 15, 2026, has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
11. A method comprising: counting a number of activations of a row; storing the number of activations in a plurality of count value memory cells; activating an alert signal when the number of activations reaches a threshold value; and performing a targeted refresh operation, wherein the targeted refresh operation is performed responsive to the number of activations reaching the threshold value.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
As can be seen from the above table, claim 11 is similar to claim 1 of patent ‘813. The
application’s method requires counting how many times a specific row (word line) is activated. The patent ‘813 discloses a "count control circuit configured to... receive a value... when the word line is activated" and "count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines." It is noted that a row in a memory array is structurally a "word line." The patent explicitly tracks and processes a value representing the "number of activations" of these word lines when they are activated, which structurally implements the concept of counting row activations.
In the application, the counted activations must be saved in a specific type of memory cell
designated for count values. The patent explicitly discloses a memory array comprising "a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines.” The patent utilizes the exact same structural components ("count value memory cells") to perform the exact same storage function (storing the activation numbers).
In the application, an alert or notification must be triggered once the activation count hits or
passes a certain limit. The patent discloses a count control circuit configured to "compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value." The "trigger signal" in the patent corresponds directly to the "alert signal" in the application. Furthermore, the condition "equal to or greater than the threshold value" inherently satisfies and encompasses the concept of the number "reaching a threshold value."
In the application, a specific refresh operation targeted at a row/adjacent rows must be
executed as a direct result of the alert signal being triggered by the threshold breach. The patent discloses a "refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received." The application shows: the targeted refresh happens responsive to the count reaching the threshold (which triggers the alert). Similarly, the patent shows: the refresh control circuit executes the "targeted refresh operation" precisely when it receives the active "trigger signal" (which, as established in the previous step, is only activated when the threshold is reached or exceeded). Therefore, coverage has already been given to the earlier filed patent application.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
13. A method comprising: counting a number of activations of a row; storing the number of activations in a plurality of count value memory cells: activating an alert signal when the number of activations reaches a threshold value; and performing a targeted refresh operation, wherein the targeted refreshes are performed on rows having a different physical relationship to the row.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
As can be seen from the above table, claim 13 is similar to claim 1 of patent ‘813. The application requires "counting a number of activations of a row". The patent shows "...store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines..." it is noted that a "row" is physically accessed and activated via a "word line." The patent explicitly tracks and stores the number of activations for these word lines.
The application requires "storing the number of activations in a plurality of count value memory cells". The patent shows "...each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values..." Both explicitly use the exact same structural concept: storing the activation counts inside a "plurality of count value memory cells" associated with the row/word line.
The application requires "activating an alert signal when the number of activations reaches a threshold value". The patent shows "...compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value...". The application's "alert signal" structurally maps to the patent's "trigger signal." The patent specifies the exact logic for how this is done (comparing the stored value to a threshold and activating the signal when it is equal to or greater), fulfilling the concept of "reaching a threshold value."
The application requires "performing a targeted refresh operation..." The patent shows "...perform a targeted refresh operation when the active trigger signal is received." Both explicitly target the mitigation of Row Hammer by executing a "targeted refresh operation" triggered by the activation count reaching its limit.
The application requires "...wherein the targeted refreshes are performed on rows having a different physical relationship to the row." The patent shows "...configured to latch a current row address and perform a targeted refresh operation..." While the patent does not explicitly use the words "different physical relationship," the concept is inherently present. A "targeted refresh" in memory architecture (Row Hammer) inherently means refreshing the victim rows (physically adjacent/neighboring rows) rather than the aggressor row itself (the "current row address" that was latched). Refreshing the current row would be useless; therefore, the apparatus latching the current address to target a refresh inherently represents performing refreshes on rows with a different physical relationship (i.e., adjacent rows). Therefore, coverage has already been given to the earlier filed patent application.
Claims 14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
14. A method comprising: provide a row activation command for a row from a controller to a memory device; and receive an active alert signal from the memory device, wherein the active alert signal indicates a number of activations of the row has reached a threshold value; and providing a precharge command a time after providing the row activation command.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
4. The apparatus of claim 1, wherein the count control circuit is further configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received.
15. The method of claim 14, further comprising providing the threshold value to the memory device.
See claim 1 and the remarks below.
17. The method of claim 15, further comprising providing a refresh command to the memory device.
See claim 1 and remarks below.
As can be seen from the above table, claim 14 of the application recites, "provide a row
activation command for a row from a controller to a memory device". Claim 1 of the patent discloses a "count control circuit configured to receive ... when the word line [row] is activated". In semiconductor memory architectures, a row is selected and activated by providing an activation command from a controller (e.g., memory controller) to the memory device. Because claim 1 of the patent includes a count control circuit that evaluates a word line when it is activated, claim 1 of the patent inherently anticipates the step of providing an activation command to initiate this process.
Claim 14 of the application recites, "receive an active alert signal from the memory device". Claim 1 of the patent features a "count control circuit configured to ... compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value". An active alert signal in, claim 14 of the application, is a signal sent upon reaching a row activation threshold. Similarly, the "trigger signal" in claim 1 of the patent is activated (and subsequently sent or received internally in the apparatus) when the threshold value is reached. This satisfies the alert signal functionality.
Claim 14 of the application recites, "wherein the active alert signal indicates a number of
activations of the row has reached a threshold value.” Claim 1 of the patent includes "a plurality of count value memory cells configured to store a plurality of values each representing a number of activations ... compare the value to a threshold value and activate a trigger signal when ... equal to or greater than the threshold value". Both claims rely on the identical logical trigger condition: tracking row activations and determining when they meet or exceed a specific threshold limit. Therefore, claim 1 of the patent describes exactly how this alert signal state is generated and indicated. Because claim 1 of the patent describes all the functional limitations of claim 14 of the application. While claim 14 of the application is framed as a method (what the system does) and claim 1 of the patent as an apparatus (the physical device), apparatus claims that include "configured to" language are typically treated as structural equivalents to corresponding methods of operation. Claim 1 of the patent explicitly covers the controller, memory device actions, and row activation monitoring necessary to perform claim 14 of the application. Therefore, coverage has been given to the earlier filed patent application.
With respect to claim 15, claim 15 of the application recites, “"providing the threshold value to the memory device". Claim 1 of the patent’s count control circuit is configured to "compare the value to a threshold value." In order for the circuit to perform this comparison, the threshold value must inherently be provided to or stored within the memory device itself. Claim 1 of the patent dictates that the hardware apparatus must store and evaluate a "threshold value." Without the ability to receive, program, or access this threshold value, claim 1 of the patent's claim limitation requiring a circuit to "compare the value to a threshold value" could not function. Therefore, the provision of the threshold value is an inherent structural and operational requirement of the claim 1 of the patent apparatus, making claim 15 of the application obvious or anticipated in light of claim 1 of the patent.
With respect to claim 14, claim 14 of the application recites, “Providing a precharge command a time after providing the row activation command.” The combination of claims 1 and 4 of the patent include "a count control circuit configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received." In standard memory operations (e.g., DRAM), memory controllers must issue a precharge command after activating a row. The combination of claims 1 and 4 inherently require a precharge command to execute its own "update" step. Therefore, providing a precharge command after an activation command is a standard, required mechanism in the memory architecture described in the combination, making it proper to reject claim 16 of the application as it lacks a novel or unexpected distinction over the combination of the claims of the patent's standard operational flow. Therefore, coverage has already been given to the earlier filed patent application.
With respect to claim 17, claim 17 of the application recites, “providing a refresh command to the memory device”. Claim 1 of the patent recites, “"...activate a trigger signal when the value is equal to or greater than the threshold value... latch a current row address and perform a targeted refresh operation..." While claim 1 of the patent recites generating an internal "trigger signal" to perform a targeted refresh, providing a refresh command (which triggers internal refresh circuitry) is structurally and functionally synonymous. Therefore, it is proper to reject claim 17 of the application because the hardware components (count control circuit and refresh control circuit) of claim 1 of the patent natively execute a targeted refresh operation based on their internal metrics. An apparatus claim inherently encompasses the method of using the apparatus. When a device like claim 1 of the patent includes control circuitry configured to perform a targeted refresh operation, a method claim reciting "providing a refresh command to the memory device" covers the exact physical operation that claim 1 of the patent performs. Thus, coverage has already been given to the earlier filed patent application.
Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 12217813 [‘813]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘813
18. An apparatus comprising: a memory controller configured to: receive an active alert signal from a memory device, wherein the active alert signal indicates a number of activations of a row has reached a threshold value; and provide the threshold value to the memory device.
1. An apparatus comprising: a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines; a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
19. The apparatus of claim 18, wherein the controller is further configured to provide a row activation command and a precharge command to the memory device.
4. The apparatus of claim 1, wherein the count control circuit is further configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received.
20. The apparatus of claim 18, wherein the controller is further configured to provide a refresh command to the memory device.
See claim 1 and remarks below.
Claim 18 of the application recites, “An apparatus comprising: a memory controller configured to..." Claim 1 of the patent outlines an apparatus (memory system) with corresponding control circuits (e.g., count control circuit, refresh control circuit) that operate as a memory controller. Claim 18 of the application recites, “"...receive an active alert signal from a memory device..." Claim 1 of the patent discloses a "trigger signal" (active alert) activated by the count control circuit when the row's activation value reaches or exceeds the threshold. Claim 18 of the application recites, "...wherein the active alert signal indicates a number of activations of a row has reached a threshold value..." Claim 1 of the patent's trigger signal is activated when a counted "number of activations of a corresponding one of the plurality of word lines" equals or exceeds a "threshold value." Claim 18 of the application recites, "...and provide the threshold value to the memory device." Claim 1 of patent's count control circuit must have access to or store this threshold value to perform the comparison operation ("compare the value to a threshold value"), inherently providing/applying it. Claim 18 of the application is an apparatus claim reciting functional capabilities that map perfectly onto the built-in control circuits (count control/refresh control) of Claim 1 of the patent. Because the specific operations (counting activations, comparing to a threshold, and triggering an alert) are identically disclosed in Claim 1 of the patent, the limitations of claim 18 of the application do not present a distinct invention, rendering it unpatentable over claim 1 of the patent. Coverage has already been given to the earlier filed patent application.
With respect to claim 19, claim 19 of the application recites, “Providing a precharge command a time after providing the row activation command.” The combination of claims 1 and 4 of the include "a count control circuit configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received." In standard memory operations (e.g., DRAM), memory controllers must issue a precharge command after activating a row. The combination of claims 1 and 4 inherently require a precharge command to execute its own "update" step. Therefore, providing a precharge command after an activation command is a standard, required mechanism in the memory architecture described in the combination, making it proper to reject claim 19 of the application as it lacks a novel or unexpected distinction over the combination of the claims of the patent's standard operational flow. Therefore, coverage has already been given to the earlier filed patent application.
With respect to claim 20, claim 20 of the application recites, “providing a refresh command to the memory device”. Claim 1 of the patent recites, “"...activate a trigger signal when the value is equal to or greater than the threshold value... latch a current row address and perform a targeted refresh operation..." While claim 1 of the patent recites generating an internal "trigger signal" to perform a targeted refresh, providing a refresh command (which triggers internal refresh circuitry) is structurally and functionally synonymous. Therefore, it is proper to reject claim 20 of the application because the hardware components (count control circuit and refresh control circuit) of claim 1 of the patent natively execute a targeted refresh operation based on their internal metrics. An apparatus claim inherently encompasses the method of using the apparatus. When a device like claim 1 of the patent includes control circuitry configured to perform a targeted refresh operation, a method claim reciting "providing a refresh command to the memory device" covers the exact physical operation that claim 1 of the patent performs. Thus, coverage has already been given to the earlier filed patent application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 1, Bains et al. disclose a memory device [pars. 0050, 0066 and 0081-0082]
comprising: a memory array comprising a plurality of rows ["...mechanisms can include keeping a count for only a subset of all rows, instead of keeping a count for all rows." It is noted that a memory device that contains "all rows" or a "subset of all rows" inherently possesses a memory array organized into a plurality of rows.], wherein each row of the plurality of rows comprises a plurality of count value memory cells configured to store a count value representing a number of activations of a corresponding one of the plurality of rows ["Some mechanisms can include keeping a count... Some mechanisms maintain a table... Some mechanisms can be based on a computed maximum victim count (MVC).". It is noted that Bains et al. discloses tracking and "keeping a count" of row accesses (activations). While the application specifies storing these counts in "count value memory cells" inside each row, it is noted that storing a row's counters within designated cells of that same row is a standard hardware implementation for "keeping a count." Further, Bain et al.’s disclosure of a "table" or "maximum victim count" covers row-level tracking structures. Furthermore, Bains et al. notes that an "Access log 312 can be implemented as a list or array or table or other logical structure that stores entries having multiple fields of information." If this access log is located on the memory device to enable it to detect the event, it satisfies the tracking of activation counts. While the Bains et al. do not explicitly use the words "cells within each row," mapping an "array or table" that stores tracking counts for corresponding rows is an equivalent or an inherent structural requirement to achieve the stated function of threshold detection.]; and an alert pin configured to provide an active alert signal when a number of activations of a row of the plurality of rows reaches a threshold value [Bains et al. explicitly states that "If the threshold of number of accesses is reached in the given time window, the memory device (e.g., via a C/A register device) sends the alert signal to the host (e.g., to the memory controller)". – pars. 0081-0082. It is noted that Bains et al discloses the exact functional limitation: detecting when a threshold of row accesses (activations) is reached and sending an alert signal from the memory device to the host. It is noted that when an alert signal leaving a chip requires a physical terminal. Therefore, it is inherently disclosed or structurally obvious that this signal is driven through a physical pin (e.g., an alert pin or an existing pin repurposed for an alert function like on a Command/Address register device).] wherein the memory device is configured to perform targeted refreshes and the targeted refreshes are performed on rows physically adjacent to the row of the plurality of rows [Bains et al. states that when the host receives the alert, "the memory controller triggers a targeted refresh in the memory device for a victim row for the row hammer condition." -Pars. 0081-0082. It is noted that a "victim row" in a Row Hammer context refers to the physically adjacent rows vulnerable to charge leakage caused by activations of an aggressor row. While Bains et al. notes that the controller triggers it, the action of performing the targeted refresh is executed in/by the memory device. This satisfies the limitation that the memory device is configured to perform targeted refreshes on adjacent rows].
With respect to claim 2, Bains et al. disclose a mode register configured to store the threshold
value [“…The detection logic obtains the threshold from a register…” – par. 0018].
Claim(s) 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 6, Bains et al. disclose a memory device [pars. 0050, 0066 and 0081-0082]
comprising: a memory array comprising a plurality of rows [Bains et al. discusses a "memory device" and tracking "accesses" (activations) to a "victim row". A memory device that tracks row-level accesses inherently consists of a memory array with a plurality of rows.], wherein each row of the plurality of rows comprises a plurality of count value memory cells configured to store a count value representing a number of activations of a corresponding one of the plurality of rows [Bains et al. states that the system determines row hammer conditions based on a "threshold of number of accesses... reached in the given time window." To know if a threshold number of accesses is reached for a specific row, the system must track the count. It is noted that while Bains et al. note that an "Access log 312 can be implemented as a list or array or table or other logical structure that stores entries," mapping this inside the memory cells of each row (as in the application) is a predictable implementation. If the physical location of the tracking structure is interpreted broadly, the "array or table" in Bains et al. covers this tracking.]; and an alert pin configured to provide an active alert signal when a number of activations of a row of the plurality of rows reaches a threshold value [Bains et al. states: "If the threshold of number of accesses is reached in the given time window, the memory device (e.g., via a C/A register device) sends the alert signal to the host...". It is noted that Bains et al. teaches a memory device sending an "alert signal" when a "threshold of number of accesses is reached." While Bains et al. mention a "C/A register device" as an example mechanism, hardware alert signals transmitted between a memory device and a host controller inherently require a physical hardware interface (an alert pin or terminal) to exit the chip. Therefore, the alert pin function is fully anticipated.], wherein the memory device is configured to perform refreshes on the plurality of rows, wherein the targeted refreshes refresh the count value memory cells of the plurality of rows [Bains et al. teaches: "When the memory controller receives an indication of a row hammer condition from the memory device, the memory controller triggers a targeted refresh in the memory device for a victim row...". It is noted that Bains et al. show the execution of "targeted refresh" operations in response to the alert. By executing a targeted refresh or standard refresh on rows structurally restores the state of those rows (and their corresponding logical/physical structures).].
Claim(s) 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 7, Bains et al. disclose a method [pars. 0050, 0066 and 0081-0082] comprising: counting a number of activations of a row [Bains et al. disclose programming "threshold values for what number of accesses triggers a row hammer event" and checking "if the threshold of number of accesses is reached."]; storing the number of activations in a plurality of count value memory cells [Bains et al. states that the system determines row hammer conditions based on a "threshold of number of accesses... reached in the given time window." To know if a threshold number of accesses is reached for a specific row, the system must track the count. It is noted that while Bains et al. note that an "Access log 312 can be implemented as a list or array or table or other logical structure that stores entries," mapping this inside the memory cells of each row (as in the application) is a predictable implementation. If the physical location of the tracking structure is interpreted broadly, the "array or table" in Bains et al. covers this tracking.]; activating an alert signal when the number of activations reaches a threshold value [Bains et al. states that if the threshold number of accesses is reached, the memory device "sends the alert signal to the host."], and performing a targeted refresh operation, wherein the targeted refreshes are performed on rows physically adjacent to the row [Bains et al. teaches: "When the memory controller receives an indication of a row hammer condition from the memory device, the memory controller triggers a targeted refresh in the memory device for a victim row...". It is noted that Bains et al. show the execution of "targeted refresh" operations in response to the alert. By executing a targeted refresh or standard refresh on rows structurally restores the state of those rows (and their corresponding logical/physical structures).].
With respect to claim 8, Bains et al. disclose storing the threshold value in a mode register [“…The detection logic obtains the threshold from a register…” – par. 0018].
With respect to claim 9, Bains et al. disclose receiving the threshold value from a controller [“a host system (e.g., via the memory controller or other logic), detects and programs the memory module row hammer threshold.” – par. 0063].
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 11, Bains et al. disclose a method comprising: counting a number of
activations of a row [Bains et al. states that "the memory controller configures the memory device to detect row hammer events" and "programs the threshold values for what number of accesses triggers a row hammer event." – pars. 0081-0082. It is noted that a "row hammer event" is caused by repeated row activations (accesses). For a device to determine if a "number of accesses" has reached a specific "threshold value," it must inherently or expressly perform the step of counting the number of activations of a row.]; storing the number of activations in a plurality of count value memory cells [Bains et al. notes that the controller can program threshold values "in a register control word" and that the memory device detects this via a "C/A [Command/Address] register device." – pars. 0081-0082. It is noted that Bains et al. explicitly mentions storing the threshold in a register, the tracking of the current number of accesses to compare against that threshold inherently requires hardware storage. A register or an internal tracking mechanism in a memory device is structurally composed of a plurality of count value memory cells (such as latches, flip-flops, or SRAM cells) used to hold the counting data. Therefore, this step is at least inherently disclosed or an obvious design choice for implementing the counting logic described in Bains et al.]; activating an alert signal when the number of activations reaches a threshold value [Bains et al. states: "If the threshold of number of accesses is reached in the given time window, the memory device (e.g., via a C/A register device) sends the alert signal to the host..." – pars. 0081-0082]; and performing a targeted refresh operation, wherein the targeted refresh operation is performed responsive to the number of activations reaching the threshold value [Bains et al. states: "When the memory controller receives an indication of a row hammer condition from the memory device, the memory controller triggers a targeted refresh in the memory device for a victim row..." – pars. 0081-0082].
Claim(s) 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 13, Bains et al. disclose a method comprising: counting a number of
activations of a row [Bains et al. describes detecting "row hammer events" based on a "number of accesses" within a "given time window." In semiconductor memory, "accesses" to a row inherently requires or implies "activations" of that row. To determine if a specific "number of accesses" has been reached, the system must inherently count them – par. 0081] ; storing the number of activations in a plurality of count value memory cells [While Bains et al. does not explicitly use the words "count value memory cells," it states that the memory controller programs threshold values and time windows into a "register control word." To track whether a threshold is reached, the device must maintain a running count. In digital logic and memory architecture, any hardware counter or tracking mechanism inherently relies on a plurality of memory cells (flip-flops, registers, or latches) to store that count value. This is an inherent characteristic or a standard, obvious implementation of a hardware counter. – par. 0081]: activating an alert signal when the number of activations reaches a threshold value [Bains et al. explicitly states, "If the threshold of number of accesses is reached... the memory device... sends the alert signal to the host." – par. 0081]; and performing a targeted refresh operation, wherein the targeted refreshes are performed on rows having a different physical relationship to the row[“With distributed detection logic, the memory devices themselves can undertake some of the operations related to identifying hammered rows and the victim row(s), as well one or more operations related to generating a targeted refresh command.” – par. 0089].
Claim(s) 14, 15 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 14, Bains et al. disclose a method comprising: provide a row activation command for a row from a controller to a memory device [Bains et al. states that the "memory controller configures the memory device to detect row hammer events." It further specifies that this detection is based on the "number of accesses" to a row. – par. 0081]; receive an active alert signal from the memory device, wherein the active alert signal indicates a number of activations of the row has reached a threshold value [Bains et al. explicitly states: "If the threshold of number of accesses is reached in the given time window, the memory device... sends the alert signal to the host (e.g., to the memory controller)." – par. 0081]; and providing a precharge command a time after providing the row activation command [Bains et al. discusses managing these accesses within a "time window" (such as a programmable "refresh window" or a window "different than the refresh window") – par. 0081].
With respect to claim 15, Bains et al. discloses providing the threshold value to the memory device [“...the memory controller can program the threshold values for what number of accesses triggers a row hammer event in a register control word.” – par. 0081]. It is noted that when a memory controller "programs" a value into a register control word located on or within a memory device, it inherently and necessarily provides that threshold value to the memory device.
With respect to claim 17, Bains et al. discloses providing a refresh command to the memory device [“the memory devices themselves can undertake some of the operations related to identifying hammered rows and the victim row(s), as well one or more operations related to generating a targeted refresh command.” – par. 0089].
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains et al. [US Patent Application # 20140156923].
With respect to claim 18, Bains et al. disclose an apparatus comprising: a memory controller configured to [Bains et al. explicitly discloses a "memory controller" that performs various configurations and actions within a memory subsystem. – par. 0081]: receive an active alert signal from a memory device [Bains et al. states: "the memory device... sends the alert signal to the host (e.g., to the memory controller)." If the memory device sends it to the memory controller, the memory controller inherently receives it. – par. 0081], wherein the active alert signal indicates a number of activations of a row has reached a threshold value [Bains et al. explains that "the memory controller configures the memory device to detect row hammer events" and that "If the threshold of number of accesses is reached... the memory device... sends the alert signal". In memory architecture, a "row hammer event" or "access" to a row is structurally driven by row activations. Therefore, reaching the threshold of accesses is identical to reaching the threshold of activations that triggers the alert. – par. 0081]; and provide the threshold value to the memory device [Bains et al. states: "the memory controller can program the threshold values... in a register control word" of the memory device. "Programming" a value into a device's register is a direct, standard technical method for a controller to "provide" a value to that device. – par. 0081]. It is noted that Bains et al. explicitly identifies both architectural components: the memory controller (host) and the memory device. The functional relationship is identical: The controller sends (provides/programs) the threshold value to the device's register control word. The device tracks row accesses (activations), and once that threshold is hit, it loops back and sends an alert signal received by the controller.
With respect to claim 19, Bains et al. disclose the controller is further configured to provide a row activation command and a precharge command to the memory device [“the memory controller sends a targeted refresh command, which the memory device separates into one or more groups of Activate and Precharge commands.” – par. 0087].
With respect to claim 20, Bains et al. disclose the controller is further configured to provide a refresh command to the memory device ]” the memory controller sends a targeted refresh command, which the memory device separates into one or more groups of Activate and Precharge commands. Other commands could be doubled-up for targeted refresh purposes.” – par. 0087].
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claim 3 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Bains et al. [US Patent
Application # 20140156923] in view of Nakano et al. [U.S. Patent Application # 20120069626].
Bains et al. disclose a memory device [pars. 0050, 0066 and 0081-0082] comprising: a memory
array comprising a plurality of rows ["...mechanisms can include keeping a count for only a subset of all rows, instead of keeping a count for all rows." It is noted that a memory device that contains "all rows" or a "subset of all rows" inherently possesses a memory array organized into a plurality of rows.], wherein each row of the plurality of rows comprises a plurality of count value memory cells configured to store a count value representing a number of activations of a corresponding one of the plurality of rows ["Some mechanisms can include keeping a count... Some mechanisms maintain a table... Some mechanisms can be based on a computed maximum victim count (MVC).". It is noted that Bains et al. discloses tracking and "keeping a count" of row accesses (activations). While the application specifies storing these counts in "count value memory cells" inside each row, it is noted that storing a row's counters within designated cells of that same row is a standard hardware implementation for "keeping a count." Further, Bain et al.’s disclosure of a "table" or "maximum victim count" covers row-level tracking structures. Furthermore, Bains et al. notes that an "Access log 312 can be implemented as a list or array or table or other logical structure that stores entries having multiple fields of information." If this access log is located on the memory device to enable it to detect the event, it satisfies the tracking of activation counts. While the Bains et al. do not explicitly use the words "cells within each row," mapping an "array or table" that stores tracking counts for corresponding rows is an equivalent or an inherent structural requirement to achieve the stated function of threshold detection.]; and an alert pin configured to provide an active alert signal when a number of activations of a row of the plurality of rows reaches a threshold value [Bains et al. explicitly states that "If the threshold of number of accesses is reached in the given time window, the memory device (e.g., via a C/A register device) sends the alert signal to the host (e.g., to the memory controller)". – pars. 0081-0082. It is noted that Bains et al discloses the exact functional limitation: detecting when a threshold of row accesses (activations) is reached and sending an alert signal from the memory device to the host. It is noted that when an alert signal leaving a chip requires a physical terminal. Therefore, it is inherently disclosed or structurally obvious that this signal is driven through a physical pin (e.g., an alert pin or an existing pin repurposed for an alert function like on a Command/Address register device).] wherein the memory device is configured to perform targeted refreshes and the targeted refreshes are performed on rows physically adjacent to the row of the plurality of rows [Bains et al. states that when the host receives the alert, "the memory controller triggers a targeted refresh in the memory device for a victim row for the row hammer condition." -Pars. 0081-0082. It is noted that a "victim row" in a Row Hammer context refers to the physically adjacent rows vulnerable to charge leakage caused by activations of an aggressor row. While Bains et al. notes that the controller triggers it, the action of performing the targeted refresh is executed in/by the memory device. This satisfies the limitation that the memory device is configured to perform targeted refreshes on adjacent rows].
Bains et al. discloses all the above-mentioned but is silent about the memory cells configured to store information to detect errors in the count value. The application requires "memory cells configured to store information." The Nakano et al. reference explicitly specifies "information stored in the memory cell... in the memory cell array." – par. 0057. Both teach the fundamental structural capability of memory cells holding data. The application dictates that this information is used "to detect errors in the count value." The Nakano et al. reference establishes that the information is "related to the error counter." [par. 0057]. A counter's structural job is to maintain a "count value." Therefore, storing data related to an error counter directly encompasses storing information used to manage, track, or detect errors inherent to that count value or counting process. While the wording differs slightly, a person having ordinary skill in the art (PHOSITA) would recognize that reading information "related to the error counter" to manage errors functionally achieves the exact objective of using stored information "to detect errors in the count value."
Bains et al. describes a structural memory array but may be silent on how it handles data corruption, tolerance, or tracking operational metrics (like errors). A PHOSITA looking at the Bains et al. reference's memory array would look for ways to make that memory more reliable. The Nakano et al. reference provides a known solution for tracking reliability: utilizing memory cells to store information related to an error counter. Therefore, it would have been obvious to one of ordinary skill in the art would incorporate the Nakano et al. reference's error-tracking capability into the Bains et al. reference's structural array to improve data integrity, fault tolerance, and system diagnostics.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 22, 2026
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