Prosecution Insights
Last updated: July 17, 2026
Application No. 18/988,551

STORAGE DEVICE PERFORMING PRE-PROGRAM OPERATION AND PROGRAM METHOD THEREOF

Final Rejection §103
Filed
Dec 19, 2024
Priority
Jul 08, 2024 — RE 10-2024-0089366
Examiner
BLUST, JASON W
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
9m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
224 granted / 283 resolved
+24.2% vs TC avg
Strong +16% interview lift
Without
With
+16.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
309
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
78.1%
+38.1% vs TC avg
§102
13.2%
-26.8% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 283 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive. The applicant presents arguments that the amended claim language is not taught and/or made obvious by the prior art on pages 7-9 of the remarks. The examiner disagrees, of which details can be found in the rejection below. In addition, the applicant has failed to adequately traverse the official notice taken by the examiner, and as such, is now considered applicant admitted prior art (AAPA). Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3, 5, 6-13, 15, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2020/0194072) in view of Hasbun (US 5,671,388). In regards to claims 1 and 9, taking claim 9 as exemplary, Oh teaches A storage device comprising: (fig. 1, ¶39, storage device 30) a non-volatile memory device as a storage medium of the storage device; (fig. 1, ¶39, NVM 200) a write buffer configured to temporarily store write data requested to be written from a host; (¶169-169, fig. 23 teaches buffer memory 1220 can store data to be programmed (written) to the NVM device 1100) a digest memory configured to store digest data that writes the write data to the non-volatile memory device in a pre-program operation mode; (¶157 and fig. 21A , and fig. 20, ¶151-154 teaches control circuit programs digest data into digest blocks (digest memory) of the memory as part of a pre-programming of the data (i.e. pre-program operation mode) a storage controller configured to: (fig. 1, ¶39, memory controller 100) set a program mode of the write data as the pre-program operation mode based on [an available memory capacity of the digest memory being greater than or equal to a threshold], wherein the program mode is set from the pre-preprogram operation mode and a normal program mode, and a program operation in the normal program mode includes a general data write operation. (¶57-58 teaches that the program manager may selectively program data using a program scheme (i.e. setting a program mode), such as the digest programming scheme based at least on one of performance of the nonvolatile memory device, efficiency of storage space and credibility. The “normal” mode of operation of programming a memory cell is taught in ¶85 and 90 (i.e. a general data write operation). ¶107-109 teaches the method of performing a write using a pre-program and digest data blocks (i.e. the pre-program mode of operation) program the write data in a first area of the non-volatile memory device according to the pre-program operation mode, and generate the digest data corresponding to the write data. (fig. 20, ¶151-154 teaches control circuit programs data into pre-program blocks of the memory, and generates digest corresponding to the pre-preprogram data and programs it into digest blocks (digest memory) of the memory as part of a pre-programming of the data (i.e. pre-program operation mode) Oh may not explicitly teach set a program mode of… operation mode based on an available memory capacity of a memory being greater than or equal to a threshold], Hasbun teaches in fig. 1 and C3:6-19 that NVM can be operated in a SLC or a MLC mode. Fig. 3, C5:62-C6:11 teaches that if enough memory is available the system can write the data in the SLC mode (i.e. the mode of operation of the memory can be based on available amounts of different types of memory. It should be noted that the digest memory and the memory used to store the pre-program blocks is (or can be considered the same memory). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to modify the system of Oh to incorporate the teachings of Hasbun such that when a threshold amount of memory is available and/or unavailable that the memory can be changed to operate in a different mode of operation. The motivation is that this allows the memory to take advantage of the availability of this additional memory in a different operational mode in order to improve the performance of the memory device. In regards to claims 5 and 7, Hasbun further teach performing a re-program operation on the multi-page data stored in the pre-program block based on the available memory capacity being less than the threshold. migrating the multi-page data stored in the pre-program block to a second memory block based on the available memory capacity being less than the threshold. (C7:12-20 teaches that data written in SLC mode is rewritten to MLC during background reclamation operations. C7:21-25 teaches that this reclamation operation can be performed based on a lack of available SLC blocks (i.e. below a threshold) In regards to claim 6 and 8, Oh further teach deallocating the digest data of the pre-program data from the digest memory. deallocating digest data corresponding to the multi-page data stored in the pre-program block from the digest memory. (¶65 teaches that after the pre-programmed and digest data has been migrated, the digest block can be erased (i.e. deallocated) In regards to claim 10, Hasbun further teaches wherein based on the available memory capacity of the digest memory being less than the threshold value, the storage controller is configured to program the write data in a second area in a normal program mode. (fig. 3, if available memory isn’t available (step 310, no), then data is written in an MLC mode (i.e. a normal program mode writing data into a MLC area) In regards to claim 11, Hasbun further teaches wherein the storage controller comprises: a mode selector configured to determine the program mode according to the available memory capacity; (fig. 3, step 310 determines if the system operates in the SLC or MLC mode based on the memory available) a re-program manager configured to perform a re-program operation of pre-programmed data stored in the first area based on the available memory capacity being less than the threshold; (C7:12-20 teaches that data written in SLC mode is rewritten to MLC during background reclamation operations. C7:21-25 teaches that this reclamation operation can be performed based on a lack of available SLC blocks (i.e. below a threshold) Oh further teaches a recovery read manager configured to read out the pre-programmed data based on the digest data. (¶155 the controller (the memory controller) 100 recovers target data based on the pre-programmed data and the digest data DGD. The controller 100 may recover the target data by performing logical operation on the pre-programmed data and the digest data DGD by using a logic circuit. In regards to claim 12, Oh further teaches wherein the storage controller comprises a migration manager configured to migrate the pre-programmed data to a second area of the non-volatile memory device based on the digest data. (¶65 teaches a migration manager 180 that migrates preprogrammed and digest data) In regards to claim 13, Oh further teaches wherein the re-program manager or the migration manager is configured to invalidate the digest data corresponding to the pre-programmed data or migrated the pre-programmed data in the digest memory. (¶65 teaches after migration of the preprogrammed and digest data, the digest data block is erased (i.e. invalidated) In regards to claim 15, Oh further teaches wherein the storage controller is configured to release allocation of the write data from the write buffer after the write data is programmed in the first area. (¶169-169, fig. 23 teaches buffer memory 1220 can store data to be programmed (written) to the NVM device 1100), note a buffer implies that data is stored there temporarily) In regards to claim 21, Oh further teaches wherein the program operation in the normal program mode programs the multi-page data into the non-volatile memory device without generating digest data of the multi-page data. The “normal” mode of operation of programming a memory cell is taught in ¶85 and 90 (i.e. a general data write operation), of which digest data is not used in programming multi-page data. ¶107-109 teaches the method of performing a write using a pre-program and digest data blocks (i.e. the pre-program mode of operation) Claim(s) 2, 3, 14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2020/0194072) in view Hasbun (US 5,671,388) and AAPA. In regards to claim 3, Oh further teach generating digest data of the multi-page data; and programming the digest data of the multi-page data into the digest memory. (fig. 20, ¶151-154 teaches control circuit programs data into pre-program blocks of the memory, and generates digest corresponding to the pre-preprogram data and programs it into digest blocks (digest memory) of the memory as part of a pre-programming of the data (i.e. pre-program operation mode) Oh and Hasbun may not explicitly teach transmitting a completion message for the write request to the host after the multi-page data is programmed into the non-volatile memory device. transmitting a completion message for the write request to the host after the digest data is programmed in the digest memory. The applicant has admitted that providing an “ack” or completion message to a host system to notify the host system that data has been received and stored is well known and ubiquitous in the art prior to the effective filing date of the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the system of Oh and Hasbun in order to implement an ack/completion message to the host in order to let the host know that the data had been stored correctly and is recoverable. The motivation for making this modification is that the host may be waiting on a completion message in order to continue further processing or sending further messages, and it also keeps the host from resending the data (i.e. assuming an error state). The results of making this modification would have been predictable to one of ordinary skill in the art. In regards to claims 2, and 14 Oh and Hasbun may not explicitly teach transmitting a completion message for the write request to the host after the multi-page data is programmed into the non-volatile memory device. transmitting a completion message for the write request to the host after the digest data is programmed in the digest memory. The applicant has admitted that providing an “ack” or completion message to a host system to notify the host system that data has been received and stored is well known and ubiquitous in the art prior to the effective filing date of the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the system of Oh and Hasbun in order to implement an ack/completion message to the host in order to let the host know that the data had been stored correctly and is recoverable. The motivation for making this modification is that the host may be waiting on a completion message in order to continue further processing or sending further messages, and it also keeps the host from resending the data (i.e. assuming an error state). The results of making this modification would have been predictable to one of ordinary skill in the art. In regards to claim 16, Oh teaches receiving a write request of multi-page data from a host; (¶169-169, fig. 23 teaches buffer memory 1220 can store data (multiple pages) to be programmed (written) to the NVM device 1100 that have been received from a host (see fig. 1, host 20)) programming the multi-page data into a pre-program block of the non-volatile memory device; (fig. 20, ¶151-154 teaches control circuit programs data into pre-program blocks of the memory, and generates digest corresponding to the pre-preprogram data and programs it into digest blocks (digest memory) of the memory as part of a pre-programming of the data (i.e. pre-program operation mode) generating digest data from the multi-page data; storing the digest data in the digest memory; (fig. 20, ¶151-154 teaches control circuit programs data into pre-program blocks of the memory, and generates digest corresponding to the pre-preprogram data and programs it into digest blocks (digest memory) of the memory as part of a pre-programming of the data (i.e. pre-program operation mode) to set a program mode of the write data as the pre-program operation mode based on [an available memory capacity of the digest memory being greater than or equal to a threshold], wherein the program mode is set from the pre-preprogram operation mode and a normal program mode, and a program operation in the normal program mode includes a general data write operation. (¶57-58 teaches that the program manager may selectively program data using a program scheme (i.e. setting a program mode), such as the digest programming scheme based at least on one of performance of the nonvolatile memory device, efficiency of storage space and credibility. The “normal” mode of operation of programming a memory cell is taught in ¶85 and 90 (i.e. a general data write operation). ¶107-109 teaches the method of performing a write using a pre-program and digest data blocks (i.e. the pre-program mode of operation) Oh may not explicitly teach checking an available memory capacity of a digest memory; setting a write mode of a non-volatile memory device to a pre-program mode based on the available memory capacity being greater than a threshold value; transmitting a completion message for the write request to the host without re-programming the multi-page data. Hasbun teaches in fig. 1 and C3:6-19 that NVM can be operated in a SLC or a MLC mode. Fig. 3, C5:62-C6:11 teaches that if enough memory is available the system can write the data in the SLC mode. (i.e. the mode of operation of the memory can be based on available amounts of different types of memory. ) It should be noted that the digest memory and the memory used to store the pre-program blocks is (or can be considered the same memory). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to modify the system of Oh to incorporate the teachings of Hasbun such that when a threshold amount of memory is available and/or unavailable that the memory can be changed to operate in a different mode of operation. The motivation is that this allows the memory to take advantage of the availability of this additional memory in a different operational mode in order to improve the performance of the memory device. The combination of Oh and Hasbun may not explicitly teach transmitting a completion message for the write request to the host without re-programming the multi-page data. The applicant has admitted that providing an “ack” or completion message to a host system to notify the host system that data has been received and stored is well known and ubiquitous in the art prior to the effective filing date of the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified the system of Oh and Hasbun in order to implement an ack/completion message to the host in order to let the host know that the data had been stored correctly and is recoverable. The motivation for making this modification is that the host may be waiting on a completion message in order to continue further processing or sending further messages, and it also keeps the host from resending the data (i.e. assuming an error state). The results of making this modification would have been predictable to one of ordinary skill in the art. In regards to claim 17, Hasbun further teaches performing re-program operation on previously pre-programmed data in the pre-program block based on the available memory capacity being less than the threshold value. (C7:12-20 teaches that data written in SLC mode is rewritten to MLC during background reclamation operations. C7:21-25 teaches that this reclamation operation can be performed based on a lack of available SLC blocks (i.e. below a threshold) In regards to claim 18, Oh further teaches deallocating digest data corresponding to the previously pre-programmed data from the digest memory. (¶65 teaches that after the pre-programmed and digest data has been migrated, the digest block can be erased (i.e. deallocated) In regards to claim 19, Hasbun further teaches migrating the previously pre-programmed data in the pre-program block to a second memory block based on the available memory capacity being less than the threshold value. (C7:12-20 teaches that data written in SLC mode is rewritten to MLC during background reclamation operations. C7:21-25 teaches that this reclamation operation can be performed based on a lack of available SLC blocks (i.e. below a threshold) In regards to claim 20, Oh further teaches deallocating digest data corresponding to the previously pre-programmed data from the digest memory.  (¶65 teaches that after the pre-programmed and digest data has been migrated, the digest block can be erased (i.e. deallocated)   Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON W BLUST/Primary Examiner, Art Unit 2132
Read full office action

Prosecution Timeline

Dec 19, 2024
Application Filed
Jan 07, 2026
Non-Final Rejection mailed — §103
Feb 01, 2026
Interview Requested
Feb 10, 2026
Applicant Interview (Telephonic)
Feb 21, 2026
Examiner Interview Summary
Mar 30, 2026
Response Filed
Jun 16, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
95%
With Interview (+16.2%)
2y 4m (~9m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 283 resolved cases by this examiner. Grant probability derived from career allowance rate.

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