DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-40 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17, 27, 30, 31-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,664,070 to Lin et al. (hereafter Lin).
Regarding independent claim 16, Lin teaches a noise reduction method for mixed in-memory computing implemented as a cross-bar array of analog cells having a plurality of columns and a plurality of rows (FIG. 1: cell array 100 comprising word lines and bit lines), the method comprising:
splitting a digital multiplier into at least a most significant (MS) portion and a least significant (LS) portion (FIG. 3: e.g. splitting weight W1j into MS portion comprising W1j(3)- W1j(2), and LS portion comprising W1j(1)- W1j(0)), the LS portion being formed of L LS bits of the digital multiplier (FIG. 3: W1j(1)- W1j(0) are LS bits of multiplier 321);
for each row of the cross-bar array:
preloading an analog cell of a first column using a first analog signal representative of the MS portion (i.e. W1j(3)- W1j(2) are previously stored in corresponding memory cells);
preloading an analog cell of a second column using a second analog signal representative of the LS portion (i.e. W1j(1)- W1j(0) are previously stored in corresponding memory cells); and
driving an input conductor of the row with an analog input signal representing a multi-bit input activation (IA) value for the row (FIG. 3: drive the row with word line driver 340);
generating an MS output signal from the first column (FIG. 3: via sensing circuit SA1-CSA1, and SA2, CSA2);
generating an LS output signal from the second column (FIG. 3: via sensing circuit SA3-CSA3, and SA4, CSA4); and
determining a digital resulting value based on the MS output signal and the LS output signal (FIG. 3: via multiplier 321, 322 and adder 323).
Regarding dependent claim 17, Lin teaches that wherein said preloading, said driving, and said generating are performed in an analog domain (because the memory cells are written and read with voltage value).
Regarding dependent claim 27, Lin teaches wherein each row of analog cells is connected to one of a plurality of input conductors and each column of analog cells is connected to one of a plurality of output conductors, the cross-bar array performing matrix vector multiplication concurrently on a plurality of multi-bit input activation (IA) values to provide a partial sum for each column (see FIGS. 1 and 3).
Regarding independent claim 30, Lin teaches a noise reduction method for mixed in-memory computing implemented as a cross-bar array of analog cells having a plurality of columns and a plurality of rows (FIG. 1: cell array 100 comprising word lines and bit lines), comprising:
splitting a digital multiplier into at least a most significant (MS) portion and a least significant (LS) portion (FIG. 3: e.g. splitting weight W1j into MS portion comprising W1j(3)- W1j(2), and LS portion comprising W1j(1)- W1j(0)), the LS portion being formed of L LS bits of the digital multiplier (FIG. 3: W1j(1)- W1j(0) are LS bits of multiplier 321);
for each row of the cross-bar array:
preloading an analog cell of a first column using a first analog signal representative of the MS portion (i.e. W1j(3)- W1j(2) are previously stored in corresponding memory cells);
preloading an analog cell of a second column using a second analog signal representative of the LS portion (i.e. W1j(1)- W1j(0) are previously stored in corresponding memory cells);
slicing a multi-bit input activation (IA) value for the row into IA bits, where i is a bit position of the IA bit (FIG. 3: see split weight W1j);
for each IA bit[i]:
driving an input conductor of the row with an inherent first reference voltage when the IA bit is zero and driving the input conductor with an inherent second reference voltage when the IA bit is one (FIG. 1: word line driver 140 for activating one or more word lines, wherein logic values “0” and “1” corresponding to ground voltage and power supply voltage);
generating an MS output signal from the first column (FIG. 3: via sensing circuit SA1-CSA1, and SA2, CSA2); and
generating an LS output signal from the second column (FIG. 3: via sensing circuit SA3-CSA3, and SA4, CSA4); and
determining a digital resulting value based on both the MS output signal and the LS output signal for each IA bit[i] (FIG. 3: via multiplier 321, 322 and adder 323).
Regarding dependent claim 31, see rejection applied to claim 17 above.
Regarding dependent claims 32-33, see rejection applied to claims 10-11 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-15, 18-19, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 11,127,460 Asnaashari et al. (hereafter Asnaashari).
Regarding independent claim 1, Lin teaches a mixed analog/digital in-memory computing system with noise reduction, comprising:
a cross-bar array of analog cells for performing matrix vector multiplication (FIG. 1: cell array 100), the cross-bar array having a plurality of input conductors for each row of the cross-bar array, and a plurality of output conductors for each column of the cross-bar array (FIG. 1: word lines and bit lines);
an input peripheral circuit for converting, for each row, an input activation (IA) value into a first IA analog signal driving the input conductor of the row (FIG. 1: word line driver 140 for activating one or more word lines);
an analog-to-digital conversion circuit for converting, for each column, an output signal carried by the output conductor of the column to a digital value (FIG. 3: each bit line is coupled to a corresponding sensing circuit of sensing circuits SA1-SA4 and CSA1-CSA4, wherein sensing circuit is seen as analog-to-digital conversion circuit because it performs a function akin to ADC);
a logic operation unit for multiplying, adding, and storing the digital values from the plurality of columns (FIG 3: comprising multiplier 321, 322 and adder 323); and
an inherent control circuitry for controlling operation of the input peripheral circuit, the analog-to-digital conversion circuit, and the logic operation circuit to cause the cross-bar array to perform matrix vector multiplication (because the in-memory computation device of FIG. 3 isn’t self-operating and needs control circuitry) by splitting the digital multiplier between multiple columns (FIG. 3: e.g. weight W1j is split into values W1j(0)- W1j(3) and stored in four column as shown) and combining digital values from the multiple columns to form a resulting value (FIG. 3: via multiplier 321, 322 and adder 323)
Lin does not explicitly teach the in-memory computation device is for reducing.
Asnaashari teaches an in-memory computation device is used as dot product data filter, i.e. reducing noise.
Since Lin and Asnaashari are both from the same field of endeavor, the purpose disclosed by Asnaashari would have been recognized in the pertinent art of Lin.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that there are many applications for in-memory computation device, and one of the applications is as filter circuit to reducing noise.
Regarding dependent claim 2, Lin teaches a variable gain module electrically coupled with the plurality of output conductors to apply at least two different gains to different ones of the output signals (FIG. 3: multiplier 321 applies different gains x23, x22, x21, 1 to different output CSA1-CSA4, respectively).
Regarding dependent claim 3, Asnaashari teaches the variable gain module comprising current multiplication circuits, the control circuitry configuring the variable gain module to implement the at least two different gains (see FIG. 4 and 15:25-42).
Asnaashari teaches current multiplication circuits instead of resistive ladder or switched capacitor circuits. However, he notes that other multipliers can also be used.
Regarding dependent claim 4, Asnaashari implicitly teaches the input peripheral circuit comprising a plurality of word line digital-to-analog converters (DACs) (FIG. 20: reference and control signal generators 2018, see 25:50-58. FIG. 5 shows that D having M bits. M-bit data should be converted to suitable analog voltage for word line selection).
Regarding dependent claim 10, Asnaashari teaches each of the analog cells comprising a memristor, whereby the cross-bar array operates in a current domain (see FIG. 3A).
Regarding dependent claim 11, Asnaashari teaches each of the analog cells comprising a dynamic random access memory, whereby the cross-bar array operates in a charge domain (see 27:16-39).
Regarding dependent claims 12-15, Lin, Asnaashari and Lee do not explicitly teach recited limitations of claims. However, Examiner takes official notice that part arrangement is matter of design choice for the device to operates as a whole.
Regarding dependent claims 18-19, see rejection applied to claims 10-11 above.
Regarding depend claim 29, see rejection applied to claim 4 above.
Claims 5-6, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Asnaashari in view of US 11,714,749 to Lee et al. (hereafter Lee).
Lin and Asnaashari teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claims.
Regarding dependent claim 5, Lee teaches an in-memory computation device comprising analog-to-digital conversion circuits (see FIG. 3), wherein the analog-to-digital conversion circuits comprising a plurality of successive approximation register (SAR) analog-to-digital converters (ADC) for converting the output signal into the digital values (see 13:63-14:10).
Since Lin, Asnaashari and Lee are all from the same field of endeavor, the purpose disclosed by Lee would have been recognized in the pertinent art of Lin/Asnaashari.
It would have been obvious to a person having ordinary skill in the art at the time of the effective filing date to use a SAR ADC in the in-memory computation device of Lin/Asnaashari, because the use of a SAR ADC in such a context was a design choice within the ordinary skill in the art.
Regarding dependent claim 6, Asnaashari teaches the control circuitry controlling a digital-to-analog converter (DAC) to implement a gain on the output signal prior to the converting (FIGS. 4-5: signals read from Bit3-Bit0 go through current amplifier circuit 410 before ADC 504).
Regarding dependent claim 9, Lee teaches the analog-to-digital conversion circuit comprising an analog-to-digital converter (ADC) with an inherent resistive ladder circuit (FIG. 11: Resistive DAC 1120) that is configurable by the controller to apply a gain to the output signal prior to the converting (FIG. 10: Vref1-Vref15 of FIG. 11 are applied to ADC of FIG. 10).
Allowable Subject Matter
Claims 7-8, 20-26, 28, 34-40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 7: the control circuitry controlling the SAR ADC to capture fewer than a maximum number of bits of the SAR ADC.
With respect to dependent claim 8: the control circuitry controlling two of the plurality of SAR ADCs coupled with two of the output signals from adjacent columns of the cross-bar array to cooperate to capture a sum the two output signals after applying a gain to at least one of the two output signals.
With respect to dependent claim 20: capturing the MS output signal as a digital MS partial sum; capturing the LS output signal as a digital LS partial sum; truncating a first number of LS-bits of the MS partial sum; truncating a second number of LS-bits of the LS partial sum, wherein the second number is greater than the first number by L; and summing the MS partial sum and the LS partial sum to form the digital resulting value.
With respect to dependent claim 22: applying a first gain to the MS output signal to form an MS adjusted signal that is smaller than the MS output signal; applying a second gain to the LS output signal to form an LS adjusted signal that is smaller than the LS output signal, wherein the second gain is a factor of 2L less than the first gain; capturing the MS adjusted signal as a digital MS partial sum; capturing the LS adjusted signal as a digital LS partial sum; and summing the MS partial sum and the LS partial sum to form the digital resulting value.
With respect to dependent claim 25: applying a first gain to the MS output signal to form an MS adjusted signal that is smaller than the MS output signal; applying a second gain to the LS output signal to form an LS adjusted signal that is smaller than the LS output signal, wherein the second gain is a factor of 2L less than the first gain; summing the MS adjusted signal and the LS adjusted signal to form as a digital MS partial sum; capturing the LS adjusted signal as a digital LS partial sum; and summing the MS partial sum and the LS partial sum to form the digital resulting value.
With respect to dependent claim 28: said splitting the digital multiplier comprising splitting the digital multiplier into the MS portion, the LS portion, and a greatest-significant (GS) portion, said noise reduction method further comprising: for each row of the cross-bar array, preloading an analog cell of a third column of the cross-bar array using a third analog signal representative of the GS portion; generating an GS output signal from the third column; and determining the digital resulting value based on the GS output signal, the MS output signal, and the LS output signal.
With respect to dependent claim 34: said determining further comprising: capturing the MS output signal as a digital MS partial sum for each IA bit[i]; capturing the LS output signal as a digital LS partial sum for each IA bit[i]; truncating a first number of LS-bits of each MS partial sum; truncating a second number of LS-bits of each LS partial sum, wherein the second number is greater than the first number by L; and summing the MS partial sums and the LS partial sums to form the digital resulting value.
With respect to dependent claim 36: said determining further comprising: applying first gains to the MS output signals to form MS adjusted signals that are smaller than the corresponding MS output signal; applying second gains to the LS output signals to form LS adjusted signals that are smaller than the corresponding LS output signal, wherein the second gain is a factor of 2L less than the corresponding first gain; capturing the MS adjusted signals as digital MS partial sums; capturing the LS adjusted signals as digital LS partial sums; and summing the MS partial sums and the LS partial sums to form the digital resulting value.
With respect to dependent claim 39: said determining further comprising: applying first gains to the MS output signals to form MS adjusted signals that are each smaller than the corresponding MS output signal; applying second gains to the LS output signals to form LS adjusted signals that are smaller than the corresponding LS output signal, wherein each second gain is a factor of 2L less than the corresponding first gain; summing the MS adjusted signal and the LS adjusted signal to form as a digital MS partial sum; capturing the LS adjusted signal as a digital LS partial sum; and summing the MS partial sum and the LS partial sum to form the digital resulting value.
Conclusion
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August 5, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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