DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Power of Attorney filed on 8/6/2025.
Allowable Subject Matter
Claim 1 would be allowable if rewritten or amended to overcome the double patenting rejections, set forth in this Office action, or with the filing of an approved terminal disclaimer.
Claims 2-18 and 20 would be allowable if rewritten to overcome the double patenting rejections, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, or with the filing of an approved terminal disclaimer.
The following is a statement of reasons for the indication of allowable subject matter:
Phelps et al. (U.S. 2018/0336165) is the closest prior art reference to reading upon most, but not all of the independent claim limitations. Phelps disclosed matrix multiplication instructions with format conversions. However, Phelps failed to disclose selecting a bit array between a first- and second-bit array based on a format conversion signal and storing the selected bit array in the second register. Additionally, Phelps failed to disclose generating alignment information using the carry save adder circuitry.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 9/5/2022.
Drawings
The Examiner contends that the drawings submitted on 12/19/2024 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-2 and 19-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,210,872. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. 12,210,872 contains every element of claims 1-2 and 19-20 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
Patent 12,210,872
1. A data processing method, performed by a processing device comprising processing circuitry, the method comprising:
1. A processing device comprising processing circuitry comprising:
at least one processor comprising at least one processing element; and a shared memory shared by the at least one processor, wherein the at least one processing element is configured to cause:
receiving a format conversion signal indicating a format of floating-point numbers between a first format and a second format;
receiving a format conversion signal indicating a format of floating-point numbers between a first format and a second format,
receiving a first set of bits representing a first floating-point number, a second set of bits representing a second floating-point number, and a third set of bits representing a third floating-point number;
receiving a first set of bits representing a first floating-point number, a second set of bits representing a second floating-point number, and a third set of bits representing a third floating-point number,
converting the first set of bits to a first sign bit, a first set of exponent bits, and a first set of mantissa bits based on the format conversion signal;
converting the first set of bits to a first sign bit, a first set of exponent bits and a first set of mantissa bits based on the format conversion signal,
converting the second set of bits to a second sign bit, a second set of exponent bits, and a second set of mantissa bits based on the format conversion signal;
converting the second set of bits to a second sign bit, a second set of exponent bits and a second set of mantissa bits based on the format conversion signal,
converting the third set of bits to a third sign bit, a third set of exponent bits, and a third set of mantissa bits based on the format conversion signal;
converting the third set of bits to a third sign bit, a third set of exponent bits and a third set of mantissa bits based on the format conversion signal,
storing bits associated with the first set of exponent bits in a first register;
wherein the at least one processing element is further configured to cause: storing bits associated with the first set of exponent bits in a first register,
storing bits associated with the second set of exponent bits in a second register;
storing bits associated with the second set of exponent bits in a second register,
storing bits associated with the third set of exponent bits in a third register;
storing bits associated with the third set of exponent bits in a third register,
performing a computation operation on the first sign bit, the first set of exponent bits, the first set of mantissa bits, the second sign bit, the second set of exponent bits, the second set of mantissa bits, the third sign bit, the third set of exponent bits, and the third set of mantissa bits;
performing a computation operation on the first sign, the first set of exponent bits, the first set of mantissa bits, the second sign bit, the second set of exponent bits, the second set of mantissa bits, the third sign bit, the third set of exponent bits, and the third set of mantissa bits, and
generating alignment information, by adding the bits in the first register, the bits in the second register, and the bits in the third register; and
adding the bits in the first register, the bits in the second register, and the bits in the third register to generate alignment information,
outputting a fourth set of bits representing an output floating-point number via the computation operation based on the format conversion signal and the alignment information,
outputting a fourth set of bits representing an output floating-point number via the computation operation based on the format conversion signal, outputting the fourth set of bits based on the alignment information, and
wherein the alignment information is generated by using a carry save adder circuitry having a bit width equal to a positive margin number added by a maximum number of the number of exponent bits in the first format and the number of exponent bits in the second format and by using a carry-propagate adder adding a sum and a carry outputted from the carry save adder.
(Claim 2) wherein the alignment information is generated by using a carry save adder circuitry having a bit width equal to a positive margin number added by a maximum number of the number of exponent bits in the first format and the number of exponent bits in the second format and by using a carry-propagate adder adding a sum and a carry outputted from the carry save adder, and wherein the positive margin number is equal to or greater than 2.
selecting a bit array between a first bit array and a second bit array based on the format conversion signal, and wherein the first bit array is associated with the second set of exponent bits according to the first format, the second bit array is associated with the second set of exponent bits according to the second format, and the selected bit array is stored in the second register.
Independent claim 19 is read upon by the independent claim 1 of U.S. Patent No. 12,210,872. Dependent claims 2 and 20 are read upon by the dependent claim 2 of U.S. Patent No. 12,210,872.
Claims 1-19 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 4, and 8-22 of U.S. Patent No. 11,954,488. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. 11,954,488 contains every element of claims 1-19 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
Patent 11,954,488
1. A data processing method, performed by a processing device comprising processing circuitry, the method comprising:
1. A processing device comprising processing circuitry comprising: at least one processor comprising at least one processing element; and a shared memory shared by the at least one processor, wherein the at least one processing element is configured to cause:
receiving a format conversion signal indicating a format of floating-point numbers between a first format and a second format;
receiving a format conversion signal indicating a format of floating-point numbers between a first format and a second format,
receiving a first set of bits representing a first floating-point number, a second set of bits representing a second floating-point number, and a third set of bits representing a third floating-point number;
receiving a first set of bits representing a first floating-point number, a second set of bits representing a second floating-point number, and a third set of bits representing a third floating- point number,
converting the first set of bits to a first sign bit, a first set of exponent bits, and a first set of mantissa bits based on the format conversion signal;
converting the first set of bits to a first sign bit, a first set of exponent bits and a first set of mantissa bits based on the format conversion signal,
converting the second set of bits to a second sign bit, a second set of exponent bits, and a second set of mantissa bits based on the format conversion signal;
converting the second set of bits to a second sign bit, a second set of exponent bits and a second set of mantissa bits based on the format conversion signal,
converting the third set of bits to a third sign bit, a third set of exponent bits, and a third set of mantissa bits based on the format conversion signal;
converting the third set of bits to a third sign bit, a third set of exponent bits and a third set of mantissa bits based on the format conversion signal,
storing bits associated with the first set of exponent bits in a first register;
wherein the at least one processing element is further configured to cause: storing bits associated with the first set of exponent bits in a first register,
storing bits associated with the second set of exponent bits in a second register;
storing bits associated with the second set of exponent bits in a second register,
storing bits associated with the third set of exponent bits in a third register;
storing bits associated with the third set of exponent bits in a third register,
performing a computation operation on the first sign bit, the first set of exponent bits, the first set of mantissa bits, the second sign bit, the second set of exponent bits, the second set of mantissa bits, the third sign bit, the third set of exponent bits, and the third set of mantissa bits;
performing a computation operation on the first sign, the first set of exponent bits, the first set of mantissa bits, the second sign bit, the second set of exponent bits, the second set of mantissa bits, the third sign bit, the third set of exponent bits, and the third set of mantissa bits, and
generating alignment information, by adding the bits in the first register, the bits in the second register, and the bits in the third register; and
adding the bits in the first register, the bits in the second register, and the bits in the third register to generate alignment information, and
outputting a fourth set of bits representing an output floating-point number via the computation operation based on the format conversion signal and the alignment information,
outputting a fourth set of bits representing an output floating-point number via the computation operation based on the format conversion signal, outputting the fourth set of bits based on the alignment information, and
wherein the alignment information is generated by using a carry save adder circuitry having a bit width equal to a positive margin number added by a maximum number of the number of exponent bits in the first format and the number of exponent bits in the second format and by using a carry-propagate adder adding a sum and a carry outputted from the carry save adder.
wherein the alignment information is generated by using a carry save adder circuitry having a bit width equal to a positive margin number added by a maximum number of the number of exponent bits in the first format and the number of exponent bits in the second format and by using a carry-propagate adder adding a sum and a carry outputted from the carry save adder.
Independent claim 19 is read upon by the dependent claim 5 of U.S. Patent No. 11,954,488. Dependent claims 2-18 are read upon by the dependent claims 4 and 8-22 of U.S. Patent No. 11,954,488.
Claims 4 and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,210,872 in view of Phelps et al. (U.S. 2018/0336165).
wherein the first set of exponent bits are stored in the first register (Phelps: Figures 3-4 and 7 elements 325a-d, 402, 406, and 701-702, paragraphs 63, 65-66, 77, and 97-98)(Figures 3-4 each show a single cell of the matrix multiplication systolic array. The cell includes a weight register (i.e. first register) and activation register, each of which stores an exponent portion of the floating-point data value. A first cell of the systolic array stores the first set of exponent bits.).
wherein the format conversion signal is triggered by a machine learning model (Phelps: Figures 1C, 2, and 9 elements 106, 113, 128a-b, 200, and 902-906, paragraphs 3, 44, 49, 58, 60, 111-114, and 116)(Matrix multiplication instructions indicate a format conversion is needed from 32-bit floating point values stored in the vector register to 16- bit bfloat values used for execution by the matrix multiplication unit. The execution occurs within a neural network processing system (i.e. machine learning model).).
performing an inference of the training the machine learning model by using the fourth set of bits representing the output floating-point number (Phelps: Figure 6, paragraphs 27-28 and 31).
training the machine learning model by using the fourth set of bits representing the output floating-point number (Phelps: Figure 6, paragraphs 30-31).
Claims 13-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,210,872 in view of Phelps et al. (U.S. 2018/0336165) and in view of Official Notice.
the number of the first set of exponent bits is equal to a maximum number of the number of exponent bits in the first format and the number of exponent bits in the second format (Phelps: Figures 1C, 6, and 9 elements 128a-b, 601-603, and 904-906, paragraphs 49, 86-88, 95, and 114)(The selected vector registers for matrix multiplication operations convert the 32-bit floating-point values to 16-bit bfloat values prior to execution. Each selected vector register includes 128x8 32-bit values for conversion. Official notice is given that floating-point conversion can occur for same bit-width inputs and outputs for the advantage of executing non-native data formats. Thus, it would have been obvious to one of ordinary skill in the art to implement conversion of a different 16- bit floating point format to the native 16-bit bfloat format used by the processor.), and
the number of the first set of mantissa bits is equal to a maximum number of the number of mantissa bits in the first format and the number of mantissa bits in the second format (Phelps: Figures 1C, 6, and 9 elements 128a-b, 601-603, and 904-906, paragraphs 49, 86-88, 95, and 114)(The selected vector registers for matrix multiplication operations convert the 32-bit floating-point values to 16-bit bfloat values prior to execution. Each selected vector register includes 128x8 32-bit values for conversion. Official notice is given that floating-point conversion can occur for same bit-width inputs and outputs for the advantage of executing non-native data formats. Thus, it would have been obvious to one of ordinary skill in the art to implement conversion of a different 16- bit floating point format to the native 16-bit bfloat format used by the processor.).
wherein the first set of bits representing the first floating-point number, the second set of bits representing the second floating-point number, and the third set of bits representing the third floating-point number are included in an instruction (Phelps: Figures 2 and 9, paragraphs 60 and 116)(Official notice is given that matrix instructions include source register data within the instruction encoding for the advantage of correctly selecting the desired input data for processing. Thus, it would have been obvious to one of ordinary skill in the art to implement encoding source vector registers for the matrix multiplication operations of Phelps.).
wherein the first floating-point number, the second floating-point number, and the third floating-point number are floating-point tensors (Phelps: Figures 1C and 6 element 106, paragraphs 44, 46, 49, and 86-88)(The vector register file receives floating-point matrices (e.g. 128x8) that include 32-bit floating point values. Official notice is given input source data can include tensors for the advantage of performing image processing from input sensor data. Thus, it would have been obvious to one of ordinary skill in the art to implement input floating- point tensors within Phelps.).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without either reciting additional elements that integrate the judicial exception into a practical application or reciting additional elements that amount to significantly more than the judicial exception. Independent claim 19 recite a mental process of converting first/second/third sign/exponent/mantissa bits, performing a computation operation on the converted bits, and generating alignment information by adding first/second/third register bits. All of the claims are directed towards a process, machine manufacture, or a composition of matter.
The converting, performing computation operation, and generating alignment information by adding is a process that, under its broadest reasonable interpretation, covers a mental process of the mind with the aid of pen and paper but for the recitation of generic computer components (e.g. first/second/third registers).
This judicial exception is not integrated into a practical application. In particular, the claim only recites “first/second/third registers” to perform the “storing of bits” steps. The “first/second/third registers” are recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Therefore, this additional element doesn’t integrate the abstract idea into a practical application because it doesn’t impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. The additional elements of selecting a first/second bit array based on a format conversion signal doesn’t amount to significantly more. Thus, the claims are directed towards an abstract idea and aren’t patent eligible.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Abe (U.S. 2022/0326911), taught product-sum calculations.
Kuroiwa (U.S. 5,309,383), taught biased exponents.
Kundu et al. (U.S. 2023/0087364), taught converting tensor data on a neural network.
Chen et al. (U.S. 2021/0224069), taught floating-point conversion.
Fowers et al. (U.S. 2020/0279153), taught converting floating-point data formats.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183