DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2 – 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 8 of parent patent U.S. Patent No. 10,789,185. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by the patented claims as seen in the mappings below.
Instant Application
Parent US Patent 10,789,185
2. A memory module supporting a first data-width mode for communicating a first number of data bits and a second data-width mode for communicating a second, lesser number of data bits, the memory module comprising: a first module data port; a second module data port; a first memory component with a first-memory-component data port; a second memory component with a second-memory-component data port; and a data-buffer component including: a first delay element connected to the first-memory-component data port; a second delay element connected to the second-memory-component data port; and a switch connected to both delay elements, configured to: in the second data-width mode, selectively connect one of the first and second delay element to the first module data port to communicate the second number of data bits; and in the first data-width mode, connect the first delay element to the first module data port and the second delay element to the second module data port to communicate the first number of data bits.
1 A memory module supporting a first data-width mode in which the memory module communicates a first number of data bits in parallel and a second data-width mode in which the memory module communicates a second number of data bits less than the first number of data bits in parallel, the memory module comprising: a first module data port; a second module data port; a first memory component having a first-memory-component data port; a second memory component having a second-memory-component data port; and a data-buffer component having: a first delay element coupled to the first-memory-component data port; a second delay element coupled to the second-memory-component data port; and a switch coupled to the first delay element and the second delay element, the switch to selectively couple, in the second data-width mode to communicate the second number of data bits in parallel, either of the first delay element and the second delay element to the first module data port; and, in the first data-width mode to communicate the first number of data bits in parallel, the first delay element to the first module data port and the second delay element to the second module data port.
3. The memory module of claim 2, wherein the data-buffer component further includes a lookup table storing delay settings for the first and second delay elements.
2. The memory module of claim 1, the data-buffer component further having a lookup table storing delay settings for the first delay element and the second delay element.
4. The memory module of claim 3, wherein the data-buffer component further includes select logic coupled to the first and second delay elements, the select logic to set delays based on the delay settings.
3. The memory module of claim 2, the data-buffer component further having select logic coupled to the first delay element and the second delay element, the select logic to set delays through the first delay element and the second delay element based on the delay settings.
5. The memory module of claim 4, wherein the select logic selects between the first and second delay elements based on a rank address distinguishing the first memory component from the second memory component.
4. The memory module of claim 3, the select logic to select one of the first delay element and the second delay element responsive to a rank address distinguishing the first memory component from the second memory component.
6. The memory module of claim 4, further comprising an address-buffer component connected to the data-buffer component, where the address-buffer component controls the select logic based on memory-address signals.
5. The memory module of claim 3, further comprising an address-buffer component coupled to the data-buffer component, the address-buffer component to control the select logic responsive to memory-address signals.
7. The memory module of claim 6, where the address-buffer component controls the select logic based on chip-identification signals that differentiate between the first and second memory components.
6. The memory module of claim 5, the address-buffer component to control the select logic responsive to chip-identification signals that distinguish between the first memory component and the second memory component.
8. The memory module of claim 2, wherein the first memory component includes at least one memory die.
7. The memory module of claim 1, wherein the first memory component comprises at least one memory die.
9. The memory module of claim 8, wherein the memory die is DRAM.
8. The memory module of claim 7, wherein the memory die comprises DRAM.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 2, 3, 8 – 11, and 16 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Publication Number 2017/0256303, hereinafter “Yu”) in view of Searles et al. (US Publication Number 2009/0244997, hereinafter “Searles”).
5. As per claims 2, 10, and 18 Yu teaches a memory module and method supporting a first data-width mode for communicating a first number of data bits and a second data-width mode for communicating a second (first and second data width paragraph 47 based on upper and lower amounts), lesser number of data bits, the memory module comprising: a first module data port (interface port between 80a to 10, figure 2); a second module data port (interface port between 80b to 10, figure 2); a first memory component (memory component 84a of 80a, figure 1) with a first-memory-component data port (associated port of memory component to channel 58, figure 2, paragraph 28); a second memory component (memory component 84n of 80a, figure 1) with a second-memory-component data port (associated port of memory component to channel 58, figure 2, paragraph 28); and a data-buffer (respective data buffer for upper and lower nibble 90a, figure 2, paragraph 28) component including: a delay element connected to the first-memory-component and the second-memory-component data port (memory components are interfaced to the data buffer via port 58, with associated delay, paragraphs 30 and 39); and a switch connected to the delay element (switch coupled to the delay element paragraph 68 where, switch is seen via pre-driver 122 internal to 104a, figure 5 which is internal to the data buffer 90a details seen in figure 4), configured to: in the second data-width mode to communicate the second number of data bits; and in the first data-width mode to communicate the first number of data bits (bit communication configurations, paragraphs 28, 32, and 33).
Yu does not appear to explicitly disclose a first delay element connected to the first-memory-component data port; a second delay element connected to the second-memory-component data port; and a switch connected to both delay elements.
However, Searles discloses a first delay element (DLL 322, figure 3) connected to the first-memory-component data port (port from 210, figure 3); a second delay element (DLL 324, figure 3) connected to the second-memory-component data port (port from 210, figure 3); and a switch connected to both delay elements (switch connected to DLL to allow for switching of modes, paragraph 52), configured to: in the second data-width mode (RX mode, figure 3), selectively connect one of the first and second delay element to the first module data port to communicate the second number of data bits (mode of RX, switch handles the delay clock function, paragraphs 48 – 52, with bit configuration, paragraphs 40, 43, 64); and in the first data-width mode (TX mode, figure 3), connect the first delay element to the first module data port and the second delay element to the second module data port to communicate the first number of data bits (mode of TX, switch handles the delay clock function, paragraphs 48 – 52, with bit configuration, paragraphs 40, 43, 64).
Yu and Searles are analogous art because they are from the same field of endeavor of DRAM handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu and Searles before him or her, to modify the delay of Yu to include the delay handling of Searles because it would enhance delay handling relating to the upper and lower nibbles.
One of ordinary skill would be motivated to make such modification in order to enhance timing functionality of a memory system (paragraphs 10 and 11). Therefore, it would have been obvious to combine Searles with Yu to obtain the invention as specified in the instant claims.
6. Yu modified by the teachings of Searles as seen in claim 2 above, as per claims 3, 11, and 19, Searles teaches a memory module and method, wherein the data-buffer component further includes a lookup table storing delay settings for the first and second delay elements (figures 7 and 8).
7. Yu modified by the teachings of Searles as seen in claim 2 above, as per claims 8 and 16, Yu teaches a memory module and method, wherein the first memory component includes at least one memory die (DRAM memory die structure, figure 1, paragraph 28).
8. Yu modified by the teachings of Searles as seen in claim 2 above, as per claims 9 and 17, Yu teaches a memory module and method, wherein the memory die is DRAM (DRAM memory die structure, figure 1, paragraph 28).
Allowable Subject Matter
9. Claims 4 – 7, 12 – 15, 20, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Butt et al. has teachings of a first and second memory components with associate delays for data width mode handling for a memory module.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184