DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2013/0314636).
Regarding claim 1, Chen discloses a pixel array substrate structure (Figs. 16-25), comprising:
a substrate (100);
a first metal layer (63) over the substrate and having a plurality of scan lines (52);
a second metal layer (64) over the first metal layer and having a plurality of data lines (51), wherein the plurality of scan lines and the plurality of data lines define a plurality of pixel areas (50, 60);
a shielding electrode layer (53) over the second metal layer and comprising a plurality of shielding electrodes that are located in the plurality of pixel areas, respectively, and cover the plurality of scan lines and the plurality of data lines in a vertical projection direction of the substrate (Figs. 16-17); and
a pixel electrode layer (54) over the shielding electrode layer and having a plurality of pixel electrodes that are located in the plurality of pixel areas, respectively (Figs. 16-18).
Regarding claim 2, Chen discloses wherein one of the plurality of pixel electrodes (54) overlaps at least one of the plurality of scan lines (52) in the vertical projection direction (Figs. 16-17).
Regarding claim 4, Chen discloses wherein one of the plurality of pixel electrodes (54) overlaps at least one of the plurality of data lines (51) in the vertical projection direction (Figs. 16-17).
Regarding claim 6, Chen discloses a first pixel transistor (51) and a second pixel transistor (52), wherein a source (512) of the first pixel transistor is coupled to one of the plurality of data lines (51), and a drain (513) of the first pixel transistor is coupled to a source (522) of the second pixel transistor, and a drain (523) of the second pixel transistor is coupled to one of the plurality of pixel electrodes (54), and a gate (511) of the first pixel transistor and a gate (521) of the second pixel transistor are coupled to one of the plurality of scan lines (52) (Figs. 16-17; para. [0107]).
Regarding claim 8, Chen discloses wherein the first metal layer (63) further has a plurality of first capacitor electrodes (63’), the second metal layer (64) further has a plurality of second capacitor electrodes (64’), and the plurality of first capacitor electrodes and the plurality of second capacitor electrodes are located in the plurality of pixel areas (Figs. 16-18).
Regarding claim 9, Chen discloses an electrophoretic display device (para. [0105]), comprising:
the pixel array substrate structure (Figs. 16-25) of claim 1;
an opposite substrate structure comprising:
a second substrate; and
a common electrode layer disposed on the second substrate; and
an electrophoretic layer between the pixel electrode layer and the common electrode layer (para. [0131]).
Regarding claim 10, Chen discloses a fabrication method of a pixel array substrate structure (Figs. 16-25), comprising:
forming a first metal layer (63) over a substrate (100), the first metal layer having a plurality of scan lines (52);
forming a second metal layer (64) over the first metal layer, the second metal layer having a plurality of data lines (51), wherein the plurality of scan lines and the plurality of data lines define a plurality of pixel areas (50, 60);
forming a shielding electrode layer (53) over the second metal layer, the shielding electrode layer comprising a plurality of shielding electrodes that are located in the plurality of pixel areas, respectively, and the plurality of shielding electrodes covering the plurality of scan lines and the plurality of data lines in a vertical projection direction of the substrate (Figs. 16-17); and
forming a pixel electrode layer (54) over the shielding electrode layer, the pixel electrode layer having a plurality of pixel electrodes that are located in the plurality of pixel areas (Figs. 16-18).
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2013/0314636).
Regarding claim 5, Chen fails to explicitly disclose wherein a width of a spacing between two of the plurality of pixel electrodes that are adjacent to each other is less than or equal to 5 μm.
However, the width of the spacing is a result-effective variable which achieves a recognized result (Chen, paras. [0100-0101]). One having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to incorporate the width range to improve aperture ratio. Furthermore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a width of a spacing between two of the plurality of pixel electrodes that are adjacent to each other is less than or equal to 5 μm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP 2144.05.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2013/0314636), as applied to claim 1 above, and further in view of Zhou et al. (US 2023/0375892).
Regarding claim 3, Chen fails to explicitly disclose wherein an edge of one of the plurality of pixel electrodes is aligned with an edge of one of the plurality of data lines in the vertical projection direction.
However, Zhou discloses a pixel array substrate structure (Figs. 1-14), wherein an edge of one of the plurality of pixel electrodes (41) is aligned with an edge of one of the plurality of data lines (12) in the vertical projection direction (Figs. 2, 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein an edge of one of the plurality of pixel electrodes is aligned with an edge of one of the plurality of data lines in the vertical projection direction, as in Zhou, into the pixel array substrate structure of Chen as design choice for shielding and aperture ratio aspects.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2013/0314636), as applied to claim 1 above, and further in view of Lou et al. (US 2016/0181280).
Regarding claim 7, Chen fails to explicitly disclose wherein the second metal layer further has a plurality of scanning signal lines that are coupled to the plurality of scan lines, respectively, and the plurality of scanning signal lines are substantially parallel to the plurality of data lines.
However, Lou discloses a pixel array substrate structure (Figs. 2-9), wherein the second metal layer (para. [0026]) further has a plurality of scanning signal lines (35) that are coupled to the plurality of scan lines (32), respectively, and the plurality of scanning signal lines are substantially parallel to the plurality of data lines (31) (Figs. 2-3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the second metal layer further has a plurality of scanning signal lines that are coupled to the plurality of scan lines, respectively, and the plurality of scanning signal lines are substantially parallel to the plurality of data lines, as in Lou, into the pixel array substrate structure of Chen to provide the array substrate without a frame (Lou, para. [0028]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2013/0314636), as applied to claim 10 above, and further in view of Hua et al. (US 2022/0252955), of record in IDS.
Regarding claim 11, Chen discloses further comprising:
forming a passivation material layer (120) over the second metal layer (64); and
forming another passivation material layer (130) over the shielding electrode layer (53) (Figs. 16-17).
Chen fails to explicitly disclose forming an overcoat layer over the passivation material layer, wherein the overcoat layer has a via; and forming a through hole in the passivation material layer and the another passivation material layer, wherein the through hole passes through the passivation material layer and the another passivation material layer, and the through hole overlaps the via in the vertical projection direction.
However, Hua discloses a fabrication method of a pixel array substrate structure (Fig. 9), comprising:
forming an overcoat layer (107) over the passivation material layer (108), wherein the overcoat layer has a via (Fig. 9); and
forming a through hole in the passivation material layer and the another passivation material layer (106), wherein the through hole passes through the passivation material layer and the another passivation material layer, and the through hole overlaps the via in the vertical projection direction (Fig. 9).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate forming an overcoat layer over the passivation material layer, wherein the overcoat layer has a via; and forming a through hole in the passivation material layer and the another passivation material layer, wherein the through hole passes through the passivation material layer and the another passivation material layer, and the through hole overlaps the via in the vertical projection direction, as in Hua, into the method of Chen to provide protective insulating layers and provide necessary connection pathway to electrical signals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAISLEY L WILSON whose telephone number is (571)270-5023. The examiner can normally be reached Monday-Friday, 9:00am-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MICHAEL CALEY can be reached at 571-272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAISLEY L WILSON/Primary Examiner, Art Unit 2871
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