DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No.11,721883. Although the claims at issue are not identical, they are not patentably distinct from each other because they essentially recite the same limitations.
Claim 1 is rejected in view of claim
Claims 1, 9 and 17 of the application
Claims 1, 3 and 9 and of the 11,721,883
1. A semiconductor package, comprising:
a semiconductor die;
a first antenna element and a second antenna element disposed laterally aside the semiconductor die;
a dielectric bulk, disposed between the first antenna element and the second antenna element; and
an encapsulation layer, disposed around the semiconductor die, the at least one first antenna element, the at least one second antenna element and the dielectric bulk, wherein a sidewall of the dielectric bulk,
a sidewall of the first antenna and a sidewall of the second antenna element are flush with each other.
9. A semiconductor package, comprising:
a semiconductor die;
an encapsulation layer, laterally encapsulating the semiconductor die; a conductive wall, embedded in the encapsulation layer aside the semiconductor die; and
a plurality of conductive pillars, embedded in the encapsulation layer aside the semiconductor die, wherein the conductive wall is disposed between the semiconductor die and the plurality of conductive pillars, and the plurality of conductive pillars are arranged in a column parallel to the conductive wall.
17. A method of forming a semiconductor package, comprising: forming a first antenna element and a second antenna element side by side on a carrier; forming a dielectric bulk between the first antenna element and the second antenna element; and forming an encapsulation layer outside of the first antenna element and the second antenna element, wherein a top surface of the dielectric bulk is flush with a top surface of the encapsulation layer.
1. A semiconductor package, comprising: a semiconductor die;
an encapsulation layer, laterally encapsulating the semiconductor die; and
at least one antenna structure, embedded in the encapsulation layer aside the semiconductor die, wherein the at least one antenna structure comprises a dielectric bulk, and
a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer, wherein a top surface of the semiconductor die, a top surface of the encapsulation layer and a top surface of the at least one antenna structure are flushed with each other.
3. The semiconductor package of claim 2, wherein the emitter structure is a single solid conductive wall.
9. A semiconductor package, comprising: a semiconductor die; an encapsulation layer, laterally encapsulating the semiconductor die; at least one antenna structure, embedded in the encapsulation layer aside the semiconductor die, wherein the at least one antenna structure comprises an emitter structure and a ground structure embedded in the encapsulation layer, and the emitter structure is disposed between the ground structure and the semiconductor die, wherein a top surface of the semiconductor die, a top surface of the encapsulation layer and a top surface of the at least one antenna structure are flushed with each other; a first bump for grounding, disposed over the encapsulation layer and electrically coupled to the ground structure; and a second bump for signaling, disposed over encapsulation layer and electrically coupled to the semiconductor die and the emitter structure.
17. A method of forming a semiconductor package, comprising: forming a conductive wall and a plurality of conductive pillars on a protection layer; placing a semiconductor die on the protection layer, wherein the conductive wall is between the semiconductor die and the conductive pillars; encapsulating the semiconductor die, the conductive wall and the plurality of conductive pillars with an encapsulation layer comprising a first dielectric material; forming an antenna cavity in the encapsulation layer between the conductive wall and the conductive pillars; and filling the antenna cavity with a second dielectric material having a dielectric constant greater than a dielectric constant of the first dielectric material, so as to form an antenna structure embedded in the encapsulation layer, wherein a top surface of the semiconductor die, a top surface of the encapsulation layer and a top surface of the antenna structure are flushed with each other.
As can be seen, though the claimed languages are not identical, it would have been obvious that claims 1,3, 9 and 17 of the ‘883 patent recite all essential limitations of claim 1 of the instant invention. Thus, the patent protections have been granted to the earlier filed patent application.
Claim 2 is rejected in view of claims 1,3, 9 and 17 of the ‘883 patent.
Claim 3 is rejected in view of claims 1,3, 9 and 17 of the ‘883 patent.
Claim 4 is rejected in view of claims 1,3, 9 and 17 of the ‘883 patent.
Claim 5 is rejected in view of claims 1,3, 9 and 17 of the ‘883 patent.
Claim 6 is rejected in view of claims 1,3, 9 and 17 of the ‘883 patent.
Claim 7 is rejected in view of claims 1,3, 9 and 17 of the ‘883 patent.
Claim 8 is rejected in view of claims 6, 12 and 20 the ‘883 patent.
Claim 10 is rejected in view of claim 10 of the ‘883 patent.
Claim 11 is rejected in view of claims 1, 3, 9 and 17 the ‘883 patent.
Claim 12 is rejected in view of claims 1, 3, 9 and 17 the ‘883 patent.
Claim 13 is rejected in view of claim 14 of the ‘883 patent.
Claim 14 is rejected in view of claims 13-14 the ‘883 patent.
Claim 15 is rejected in view of claims 12-14 of the ‘883 patent.
Claim 16 is rejected in view of claims 6, 12 and 20 the ‘883 patent.
Claim 18 is rejected in view of claims 1, 3, 9 and 17 the ‘883 patent.
Claim 19 is rejected in view of claims 1, 3, 9 and 17 the ‘883 patent.
Claim 20 is rejected in view of claims 6, 12 and 20 of the ‘883 patent.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN MINH LE whose telephone number is (571)272-2396. The examiner can normally be reached 6:30-5:00 PM M-Th..
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/THIEN M LE/Primary Examiner, Art Unit 2876
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