DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claims 1-6 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the conduction states" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the state of charge" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 6 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hatular (US 6184660 B1) in view of Nagatsuka et al. (hereinafter Nagatsuka) (US 20120292680 A1).
As to claim 1, Hatular teaches a power storage device [FIG. 1A: device 20] comprising:
a power storage unit [smart battery 22];
a first transistor [transistor 62];
a second transistor [transistor 86]; and
a control circuit [FIG. 1A: battery charger IC 50] electrically connected to a gate of the first transistor, a gate of the second transistor, and the power storage unit, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor [FI. 1A: connections between battery charger IC, transistor 62, and transistor 86],
wherein the other one of the source and the drain of the second transistor is electrically connected to the power storage unit [FIG. 1A: connection line 88 between transistor 86 and smart battery 22],
wherein the control circuit includes a processor [FIG. 2: IC circuit in the battery charger IC 50],
wherein the processor includes a register [FIG. 2: register 132],
wherein the register includes a first memory circuit and a second memory circuit [FIG. 3: registers 132a-132i].
Hatular does not teach wherein the second memory circuit includes a third transistor and a fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,
wherein the third transistor includes a channel formation region which includes an oxide semiconductor, and
wherein the fourth transistor includes a channel formation region which includes a silicon.
Nagatsuka teaches that a memory includes oxide semiconductor transistor and silicon transistor, wherein one of a source and a drain of the oxide semiconductor transistor is electrically connected to a gate of the silicon transistor [abstract].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of deploying the transistors in the memory as suggested in Nagatsuka. One of ordinary skill in the art would have been motivated to make such modification to reduce power consumption of a memory device [abstract].
As to claim 2, Hatular teaches wherein the control circuit is configured to control the conduction states of the first transistor [FIG. 1A] [col. 12, lines 10-13: “Accordingly, the switch drive 162 supplies, via a HDR signal line 164 to an input of the inverting amplifier 66, a signal for turning the series switch 62 on and then off.”] and the second transistor [FIG. 1A] [col. 15, lines 16-19: “…then the comparator 226 transmits a CHGST signal to the gate terminal 86g of the reverse-current-protection switch 86 via a CHGST signal line 228 to turn the reverse-current-protection switch 86 on…”].
As to claim 3, Hatular teaches wherein the control circuit is configured to monitor the state of charge of the power storage unit [col. 8, line 21-50].
As to claim 6, Nagatsuka teaches wherein the third transistor is positioned above the fourth transistor [FIG. 20].
Claim 4 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hatular (US 6184660 B1) in view of Nagatsuka et al. (hereinafter Nagatsuka) (US 20120292680 A1), and further in view of Ohkawa et al. (hereinafter Ohkawa) (US 20120175953 A1).
As to claim 4, Hatular in view of Nagatsuka does not teach wherein the first memory circuit is configured to hold data in a period during which power is supplied to the control circuit from the power storage unit, and wherein the second memory circuit is configured to hold data in a period during which supply of the power to the control circuit from the power storage unit is stopped.
Ohkawa teaches that a battery controller includes a volatile memory [FIG. 7: RAM 1117] configured to hold data in a period during which power is supplied to the control circuit from the power storage unit [FIG. 9: steps 802 and 810] [0168: in step 802, the vehicle is started when key switch of the vehicle is actuated…”] [070: “In the next step 810, the data shown in FIG. 8 that is stored in the rewritable non-volatile memory 1116 is read out, and is transferred to the volatile memory RAM 1117.”]; and a non-volatile memory [FIG. 7: non-volatile memory 1116] configured to hold data in a period during which supply of the power to the control circuit from the power storage unit is stopped [FIG. 9: steps 846 and 860] [0179: “Next, when the operation of the vehicle ends and the key switch is turned off, in a step 846…”] [0182: “in a step 856 the battery controller 20 first stores this data in its volatile memory 1117. This data is then written into the rewritable non-volatile memory 1116 in step 860.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of deploying volatile and non-volatile memory in the battery control for storing data as suggested in Ohkawa into Hatular in view of Ikeuchi to manage power storage device. One having ordinary skill in the art would have been motivated to make such modification to improve performance of power management.
Claim 5 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hatular (US 6184660 B1) in view of Nagatsuka et al. (hereinafter Nagatsuka) (US 20120292680 A1), and further in view of Goto (US 20090121683 A1).
As to claim 5, Hatular in view of Nagatsuka does not teach wherein the third transistor includes a first gate and a second gate, wherein the first gate of the third transistor is positioned below the channel formation region of the third transistor, and wherein the second gate of the third transistor is positioned above the channel formation region of the third transistor.
Goto teaches that a transistor includes a first gate and a second gate, wherein the first gate of the transistor is positioned below the channel formation region of the third transistor, and wherein the second gate of the transistor is positioned above the channel formation region of the transistor [0032: “a BG terminal for controlling the back-gate voltage of the four-terminal back gate switching FET M1, the BG terminal being connected to the back gate of the four-terminal back gate switching FET M1; and an OUT terminal for performing on-off control on the four-terminal back gate switching FET M1, the OUT terminal being connected to the gate terminal of the four-terminal back gate switching FET M1.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of deploying a transistor with two gate as suggested in Goto into Hatular in view of Nafatsuka to implement charging and discharging control. One having ordinary skill in the art would have been obvious to one of ordinary skill in the art to make such modification to reduce occupancy space and cost by using signal transistor capable of controlling both charge and discharge [0002] [0015].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUXING CHEN whose telephone number is (571)270-3486. The examiner can normally be reached M-F 9-5:30PM.
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/XUXING CHEN/Primary Examiner, Art Unit 2176
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