Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 20, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed January 15, 2025 have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 7 of U.S. Patent No. 12224017 [‘017]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘017
1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, to perform operations comprising: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.
1. A system comprising: a memory device comprising a plurality of blocks, each block of the plurality of blocks comprising a plurality of wordlines, each wordline of the plurality of wordlines connected to a respective set of memory cells; and a processing device, operatively coupled with the memory device to perform operations comprising: responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block; responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric; and performing, using the read voltage offset, a read operation responsive to the read request.
2. The system of claim 1, wherein the metric reflects a ratio of a number of programmed wordlines associated with the set of memory cells to a total number of wordlines associated with the set of memory cells.
7. The system of claim 1, wherein the metric reflects a ratio of the number of programmed wordlines of the block to a total number of wordlines of the block.
3. The system of claim 1, wherein the metric reflects a trip point of a passthrough voltage applied to one or more unselected wordlines.
See claim 1. Measuring the programmed state of memory cells inherently relates to measuring threshold voltage shifts, which directly affects the trip points of pass/passthrough voltages applied to adjacent or unselected wordlines. Using pass voltage trip points or checking wordline programming counts are alternative, overlapping methods to detect whether a memory block is in a "partially programmed" or fully programmed state. It is obvious to use one or the other, making the application an obvious variation of the patent.
4. The system of claim 1, wherein the metric is a predefined function of a number of programmed wordlines associated with the set of memory cells.
See claim 1. The patent describes "determining a value of a metric reflective of a number of programmed wordlines of the block". Because the patent explicitly determines the offset based on the number of programmed wordlines, this metric is mathematically and logically a function of the number of programmed wordlines. Reciting the underlying logic or a mathematical relationship is equivalent to predefined function.
5. The system of claim 1, wherein determining the read voltage offset comprises: identifying, in a metadata structure, a record associating the value of the metric and the corresponding read voltage offset.
2. The system of claim 1, wherein identifying the read voltage offset comprises: identifying, in a metadata structure, a record associating the value of the metric and the corresponding read voltage offset.
6. The system of claim 1, wherein determining the read voltage offset further comprises: determining whether at least one wordline associated with the set of memory cells is connected to a corresponding subset of erased memory cells.
3. The system of claim 1, wherein determining whether the block is in a partially programmed state comprises: determining whether at least one wordline in the block is connected to a corresponding set of erased memory cells.
7. The system of claim 1, wherein the read voltage offset is computed to minimize a rate of error handling operations triggered by the memory access operation.
See claim 1. The purpose of identifying a read voltage offset based on a programmed-state metric is inherently to reduce bit errors and prevent read failures.
8. The system of claim 1, wherein performing the memory access operation further comprises: applying a passthrough voltage to one or more unselected wordlines.
See claim 1. Applying a passthrough voltage (often referred to as a V_pass in NAND flash operations) to unselected wordlines is a standard. It allows current to flow through the unselected memory cells in a string so that only the target cell's data is sensed.
As can be seen from the above table, claim 1 of the patent ‘017 has the following core specifics:
Defines a memory structure with blocks, wordlines, and sets of memory cells.
Introduces a metric for the number of programmed wordlines to determine if a block is in a partially programmed state.
Uses this state to identify a specific read voltage offset to perform a read operation.
Claim 1 of the application has the following core Specifics:
Defines a memory structure with a memory device and processing device.
Determines a read voltage offset corresponding to a metric reflective of a programmed state of a set of memory cells.
Performs a memory access operation using that read voltage offset.
Both claims share the same inventive concept: using a programmed-state metric to adjust read voltages for a memory access operation. The patent merely provides the specific implementation details (identifying a "partially programmed state" based on the number of programmed wordlines) that the application omits in an attempt to claim the concept more broadly. The application is structurally broader. It states the processing device determines a read voltage offset based on a "metric reflective of a programmed state." This broad language encompasses the exact metric described in the patent (number of programmed wordlines/partially programmed state). It is obvious to use a specific, disclosed species (the number of programmed wordlines) since the result yields the same functional outcome. Therefore, coverage has already been given to the earlier filed patent application.
For similar reasons, claims 2-8 are rejected over claims 1-3 and 7 of patent ‘017.
Claims 9-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-10 and 14 of U.S. Patent No. 12224017 [‘017]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘017
9. A method comprising: determining, by a processing device, a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.
8. A method comprising: responsive to receiving a read request that specifies a block within a plurality of blocks of a memory device, determining a value of a metric reflective of a number of programmed wordlines of the block; responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric; and performing, using the read voltage offset, a read operation responsive to the read request.
10. The method of claim 9, wherein the metric reflects a ratio of a number of programmed wordlines associated with the set of memory cells to a total number of wordlines associated with the set of memory cells.
14. The method of claim 8, wherein the metric reflects a ratio of the number of programmed wordlines of the block to a total number of wordlines of the block.
11. The method of claim 9, wherein the metric reflects a trip point of a passthrough voltage applied to one or more unselected wordlines.
See claim 8. Measuring the programmed state of memory cells inherently relates to measuring threshold voltage shifts, which directly affects the trip points of pass/passthrough voltages applied to adjacent or unselected wordlines. Using pass voltage trip points or checking wordline programming counts are alternative, overlapping methods to detect whether a memory block is in a "partially programmed" or fully programmed state. It is obvious to use one or the other, making the application an obvious variation of the patent.
12. The method of claim 9, wherein the metric is a predefined function of a number of programmed wordlines associated with the set of memory cells.
See claim 8. The patent describes "determining a value of a metric reflective of a number of programmed wordlines of the block". Because the patent explicitly determines the offset based on the number of programmed wordlines, this metric is mathematically and logically a function of the number of programmed wordlines. Reciting the underlying logic or a mathematical relationship is equivalent to predefined function.
13. The method of claim 9, wherein determining the read voltage offset comprises: identifying, in a metadata structure, a record associating the value of the metric and the corresponding read voltage offset.
9. The method of claim 8, wherein identifying the read voltage offset comprises: identifying, in a metadata structure, a record associating the value of the metric and the corresponding read voltage offset.
14. The method of claim 9, wherein determining the read voltage offset further comprises: determining whether at least one wordline associated with the set of memory cells is connected to a corresponding subset of erased memory cells.
10. The method of claim 8, wherein determining whether the block is in a partially programmed state comprises: determining whether at least one wordline in the block is connected to a corresponding set of erased memory cells.
15. The method of claim 9, wherein the read voltage offset is computed to minimize a rate of error handling operations triggered by the memory access operation.
See claim 8. The purpose of identifying a read voltage offset based on a programmed-state metric is inherently to reduce bit errors and prevent read failures.
As can be seen in the table above, claim 9 of the application is similar to claim 8 of the patent.
The claimed recitation of "a metric reflective of a programmed state..." corresponds to the patent’s "metric reflective of a number of programmed wordlines of the block." (A block's programmed wordlines define its programmed state). The claimed recitation of "identifying a read voltage offset corresponding to the value..." is directly matched by the patent's "identifying a read voltage offset corresponding to the value of the metric." The claimed recitation of "performing, using the read voltage offset, a memory access operation..." corresponds to the patent's "performing, using the read voltage offset, a read operation." (A read operation is a subset of a memory access operation). The application is significantly broader than the patent. While the patent explicitly specifies the metric is the "number of programmed wordlines of the block" and explicitly requires that the block is in a "partially programmed state," the application uses open-ended language ("a metric," "programmed state"). Because a narrower, specific embodiment (patent) reads onto a broader, generic claim (application), the generic claim is anticipated. Therefore, coverage has already been given to the earlier filed patent application.
For similar reasons, claims 10-15 are rejected over claims 8-10 and 14 of patent ‘017.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15, 16 and 20 of U.S. Patent No. 12224017 [‘017]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘017
16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a read request that specifies a block within a plurality of blocks, the block comprising a plurality of wordlines on a memory device; responsive to receiving the read request, determining a value of a metric reflective of a number of programmed wordlines of the block; responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric; and issuing, to the memory device, a read command comprising the read voltage offset.
17. The non-transitory computer-readable storage medium of claim 16, wherein the metric reflects a ratio of a number of programmed wordlines associated with the set of memory cells to a total number of wordlines associated with the set of memory cells.
20. The non-transitory computer-readable storage medium of claim 18, wherein the metric is a count of programmed wordlines of the block.
18. The non-transitory computer-readable storage medium of claim 16, wherein the metric reflects a trip point of a passthrough voltage applied to one or more unselected wordlines.
See claim 15. Measuring the programmed state of memory cells inherently relates to measuring threshold voltage shifts, which directly affects the trip points of pass/passthrough voltages applied to adjacent or unselected wordlines. Using pass voltage trip points or checking wordline programming counts are alternative, overlapping methods to detect whether a memory block is in a "partially programmed" or fully programmed state. It is obvious to use one or the other, making the application an obvious variation of the patent.
19. The non-transitory computer-readable storage medium of claim 16, wherein the metric is a predefined function of a number of programmed wordlines associated with the set of memory cells.
See claim 15. The patent describes "determining a value of a metric reflective of a number of programmed wordlines of the block". Because the patent explicitly determines the offset based on the number of programmed wordlines, this metric is mathematically and logically a function of the number of programmed wordlines. Reciting the underlying logic or a mathematical relationship is equivalent to predefined function.
20. The non-transitory computer-readable storage medium of claim 16, wherein determining the read voltage offset comprises: identifying, in a metadata structure, a record associating the value of the metric and the corresponding read voltage offset.
16. The non-transitory computer-readable storage medium of claim 15, wherein identifying the read voltage offset comprises: identifying, in a metadata structure, a record associating the value of the metric and the corresponding read voltage offset.
As can be seen from the above table, claim 16 of the application recites “Determining a read voltage offset"; whereas, Claim 15 of the patent describes "identifying a read voltage offset", which inherently requires determining it. The patent derives this offset based on "determining... a value of a metric reflective of a number of programmed wordlines" (partially programmed state). The application broadly requires a metric "reflective of a programmed state." The specific metric (number of programmed wordlines) in the patent falls entirely within the broader scope (a programmed state).
The application recites "Performing, using the read voltage offset, a memory access operation". The patent phrase explicitly specifies "issuing, to the memory device, a read command comprising the read voltage offset." A read command is a type of memory access operation. Thus, the broader limitation of the application is fully satisfied. The application applies the method to a "set of memory cells." Because a wordline is fundamentally a physical row of memory cells, applying an offset to a wordline is identical to applying it to a set of memory cells. Therefore, coverage has already been given to the earlier filed patent application.
For similar reasons, claims 17-20 are rejected over claims 15, 16 and 20 of patent ‘017.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Purahmad et al. [US Patent Application # 20200090760].
With respect to claim 1, Purahmad et al. disclose a system comprising: a memory device [108 of fig, 4]; and a processing device [102], operatively coupled to the memory device, to perform operations comprising: determining a read voltage offset [“The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage.” – Abstract] corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device [“ The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device” – Abstract]; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells [“The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.” – Abstract].
With respect to claim 7, Purahmad et al. disclose the read voltage offset is computed to minimize a rate of error handling operations triggered by the memory access operation [“The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device – Abstract].
With respect to claim 8, Purahmad et al. disclose performing the memory access operation further comprises: applying a passthrough voltage to one or more unselected wordlines. The patent states the controller determines and applies an “adjusted read level voltage to a wordline.” In non-volatile memory (like NAND Flash), a memory access operation requires distinct bias voltages to be applied to all wordlines in the target string simultaneously (i.e., the target wordline receives the read voltage, while adjacent/unselected wordlines receive the passthrough voltage so that cells are bypassed). Because the controller controls the operation, it inherently directs the voltages applied to unselected wordlines.
Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Purahmad et al. [US Patent Application # 20200090760].
With respect to claim 9, Purahmad et al. disclose a method comprising: determining, by a processing device [102 of fig. 4], a read voltage offset [“The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage.” – Abstract] corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device [“ The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device” – Abstract]; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells [“The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.” – Abstract].
With respect to claim 15, Purahmad et al. disclose the read voltage offset is computed to minimize a rate of error handling operations triggered by the memory access operation [“The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device – Abstract].
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Purahmad et al. [US Patent Application # 20200090760].
With respect to claim 16, Purahmad et al. disclose a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device [102 of fig. 4], cause the processing device to perform operations comprising: determining a read voltage offset offset [“The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage.” – Abstract] corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device [“ The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device” – Abstract]; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells [“The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.” – Abstract].
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 July 15, 2026
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