Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Talpes et al (US 2019/0026237, herein Talpes) in view of Liu et al (US 2019/0057063, herein Liu).
Regarding claim 1, teaches a method comprising:
storing, in a memory, a matrix for computation in a neural network ([0042-0043], matrix processor to perform neural network, memory 102);
obtaining one or more programming parameters for reading data elements in the matrix from the memory, the one or more programming parameters comprising a stride parameter that indicates a storage size of a memory fragment the matrix ([0092-0095], [0101], reading matrix elements according to stride parameter and other information);
determining a memory address for one or more data elements in the matrix based on the stride parameter ([0101], [0104-0105], find address according to stride parameter and other information); and
reading the one or more data elements from the memory fragment based on the memory address ([0092-0097], reading matrix elements from starting memory address).
Talpes fails to teach the matrix comprising one or more submatrices.
Liu teaches a method for storing a matrix for computation in a neural network comprising one or more submatrices and determining a memory address for one or more data elements in the submatrix based on the stride parameter (Abstract, [0023], [0026], neural network operations on submatrices and reading data elements according to stride and starting address).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Talpes and Liu to utilize the matrix operations technique on matrices that are embodied as multiple distinct submatrices. While Talpes does not explicitly disclose that the exemplary matrices in storage may be divided into submatrices, one of ordinary skill in the art would understand that doing so would merely be an implementation choice to define the boundaries of various data elements that make up the overall matrix to be operated upon. As both Talpes and Liu disclose the use of matrix computations to operate a neural network, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Talpes and Liu teaches the method of claim 1, wherein the one or more data elements in the submatrix are stored in the memory fragment sequentially (Talpes [0022-0023], elements of matrix arranged consecutively), and the one or more programming parameters further comprise an offset parameter indicating a memory address offset for a first data element stored in the memory fragment (Talpes [0073], bias parameter and results offset by bias value).
Regarding claim 3, the combination of Talpes and Liu teaches the method of claim 2, wherein determining the memory address comprises: determining the memory address based on the stride parameter and the offset parameter (Talpes [0073]).
Regarding claim 4, the combination of Talpes and Liu teaches the method of claim 1, wherein determining the memory address comprises: determining the memory address based on the stride parameter and a base address (Talpes [0095-0097], address based on stride and start element address & Liu [0059], starting address & stride parameter of submatrix).
Regarding claim 5, the combination of Talpes and Liu teaches the method of claim 1, wherein the stride parameter corresponds to a stride in data elements between consecutive rows of the matrix (Talpes [0022], [0097], loading consecutive elements & loading elements by row).
Regarding claim 6, the combination of Talpes and Liu teaches the method of claim 1, wherein the stride parameter corresponds to a stride in data elements between consecutive columns of the matrix (Talpes [0022], [0040], [0085], loading consecutive elements & loading elements by column)
Regarding claim 7, the combination of Talpes and Liu teaches the method of claim 1, wherein the stride parameter is determined based on a number of data elements along a dimension of the matrix (Liu [0039], submatrix width & height).
Regarding claim 8, the combination of Talpes and Liu teaches the method of claim 1, wherein determining the memory address comprises: determining whether a read loop comprising one or more read operations is complete (Talpes [0149], [0157-0158], looping data and weight reads).
Regarding claim 9, the combination of Talpes and Liu teaches the method of claim 8, wherein determining the memory address further comprises: after determining that the read loop is complete, determining the memory address (Talpes [0119-0120], loop back to determining start address).
Regarding claim 10, the combination of Talpes and Liu teaches the method of claim 8, wherein determining the memory address further comprises: after determining that the read loop is incomplete, holding off on determining the memory address (Talpes [0139], loop back to wait for memory access if reading is incomplete).
Claims 11-14 and 16-17 refer to a medium embodiment of the method embodiment of claims 1-4 and 7-8, respectively. Therefore, the above rejections for claims 1-4 and 7-8 are applicable to claims 11-14 and 16-17, respectively.
Claim 15 refers to a medium embodiment of the method embodiment of the limitations of claims 5 and 6. Therefore, the above rejections for claims 5 and 6 are applicable to claim 15.
Claims 18-20 refer to an apparatus embodiment of the medium embodiment of claims 11, 13, and 15. Therefore, the above rejections for claims 11, 13, and 15 are applicable to claims 18, 19, and 20, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Majnemer (US 2021/0056396) discloses a processor that loads elements of a submatrix using a stride offset value.
Das Sarma (US 2020/0349216) discloses a processor that processes elements of a matrix based on an operand size, start address, stride parameter, and padding parameter.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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