DETAILED ACTION
This action is responsive to the following: The application and the information disclosure statement filed on December 20, 2024.
Claims 21-40 are pending. Claims 21, 31, and 40 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 12, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Claims 21-40 use claim limitations: “off-module,” and “memory-module” with insufficient structure makeup of the circuit.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Such claim limitation(s) is/are:
Claim 40 uses the limitation “means for”
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 24 and 34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
These claims recite a “lack of electrical connection to the data path between the host control component and the one or more socketed memory modules.” There is no mention of this in the specification, nor do the drawings show support for such a limitation. The BCRD component of the Fig. 1 shows electrical connections to the data buffer circuits, which are understood to be in the data path between the host and memory modules.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23, 25, 28-29, 31-33, 37-38 and 40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Carlough et al (US 20190163384 A1).
Regarding Independent Claim 21, Carlough teaches an integrated-circuit control buffer (control buffer IC) comprising:
memory-module control circuitry (Fig. 3: 330) to receive memory-module control signals from a host control component and to re-transmit the memory-module control signals to one or more socketed memory modules (para 47 “The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor. The control signals may include address locations or tags on where to store data in the memory devices. The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits. ”); and
data-buffer control circuitry (Fig. 3: 332) to transmit, to one or more off-module data buffer ICs disposed in a data path between the host control component and the one or more socketed memory modules, data-buffer control signals that correspond to the memory-module control signals and enable data transfer between the host control component and the one or more socketed memory modules (para 48 “the data buffer circuits 340 buffer, receive, transmit, and/or transfer data between the Host, e.g., control processor system 302, and the memory devices 350.”).
Regarding Claim 22, Carlough teaches the limitations of claim 21. Carlough further teaches wherein the data-buffer control signals enable data transfer between the host control component and the one or more socketed memory modules (para 48 “The data buffer circuits 340 buffer, receive, transmit, and/or transfer data between the Host, e.g., control processor system 302, and the memory devices 350.”) in the form of data signals conducted via the data path and propagating through the one or more off-module data buffer ICs (para 65 “Once the memory control circuit memory scheduler 438 schedules the fetch operation to execute, the command signal and address, e.g., address (tag), is sent from the AC chip 430 over link 480 to the memory devices 450 and the DC chips 440 are informed by the AC chip 430 over link 470 that fetch data will arrive at the data buffer circuit 440 to be sent to the Host”).
Regarding Claim 23, Carlough teaches the limitations of claim 21. Carlough further teaches wherein the data path comprises a first set of data signaling links coupled between the host control component and the one or more off-module data buffer ICs and a second set of data signaling links coupled between the one or more off- module data buffer ICs and the one or more socketed memory modules (para 6 “There are communication links or buses between a Host processor and the memory control circuits and data buffer circuits. There is also a communication link or bus from the memory control circuits to the data buffer circuits. There are also communication links between the memory devices, e.g., DRAMS, and the memory control circuits and the data buffer circuits.”).
Regarding Claim 25, Carlough teaches the limitations of claim 21. Carlough further teaches wherein the memory-module control circuitry (Fig. 3: 330) comprises a control interface to receive the memory-module control signals from the host control component and a memory-module interface to (i) receive the memory-module control signals from the control interface (para 45 “a processing subsystem that includes at least one processor unit (CPU) 206 that may be configured to interface with a Memory Control Unit (MCU) 210.”) and (ii) re-transmit the memory-module control signals to the one or more socketed memory modules (para 47 “The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits.”).
Regarding Claim 28, Carlough teaches the limitations of claim 25. Carlough further teaches wherein the data-buffer control circuitry (Fig. 3: 332) comprises circuitry to receive the receive the memory-module control signals from the control interface and to generate the data-buffer control signals based at least in part on the memory-module control signals (para 47 “ The memory control circuit manages the flow of data going to and from the memory devices. The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor. The control signals may include address locations or tags on where to store data in the memory devices. The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits.”).
Regarding Claim 29, Carlough teaches the limitations of claim 21. Carlough further teaches wherein the data-buffer control circuitry (Fig. 3: 332) comprises one or more buffer communication interfaces, distinct from the control interface and the memory-module interface, to transmit the data-buffer control signals to the one or more off- module data buffer ICs. (para 8 “the communications link includes a data communications link between the Host and the at least one data buffer circuit, and the at least one data buffer circuit and the at least one memory device, and a control communications link between the memory control circuit and the at least one data buffer circuit.”)
Regarding Independent Claim 31, Carlough teaches a method of operation within an integrated-circuit control buffer (control buffer IC),the method comprising:
receiving memory-module control signals from a host control component; para 47 “The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor.”)
re-transmitting the memory-module control signals (para 47 “The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor. The control signals may include address locations or tags on where to store data in the memory devices.”) to one or more socketed memory modules (para 47 “The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits. ”); and
transmitting, to one or more off-module data buffer ICs (para 47 “The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits. ”) disposed in a data path between the host control component and the one or more socketed memory modules, data-buffer control signals that correspond to the memory-module control signals and enable data transfer between the host control component and the one or more socketed memory modules.
Regarding Claim 32, is rejected for the same reasons as claim 23.
Regarding Claim 33, Carlough teaches the limitations of claim 32. Carlough further teaches wherein transmitting the data-buffer control signals to the one or more off-module data buffer ICs to enable data transfer between the host control component and the one or more socketed memory modules comprises enabling the one or more off-module data buffer ICs to re-transmit, to the one or more socketed memory modules via the second set of data signaling links, data signals received from the host control component via the first set of data signaling links (para 47 “The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor. The control signals may include address locations or tags on where to store data in the memory devices. The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits.”).
Regarding Claim 37, Carlough teaches the limitations of claim 31. Carlough further teaches comprising generating the data-buffer control signals based at least in part on the memory-module control signals. ((para 47 “The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor. The control signals may include address locations or tags on where to store data in the memory devices. The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits.”)
Regarding Claim 38, this claim is rejected for the same reasons as claim 25.
Regarding Independent Claim 40, Carlough teaches An integrated-circuit control buffer comprising:
means for receiving memory-module control signals from a host control component (para 47 “The memory control circuit typically receives signals such as command and control signals from a Host, e.g., a Host processor. The control signals may include address locations or tags on where to store data in the memory devices.”);
means for re-transmitting the memory-module control signals to one or more socketed memory modules (para 47 “The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits. ”); and
means for transmitting, to one or more off-module data buffer ICs (para 47 “The memory control circuit may output command and control signals to the memory devices and/or data buffer circuits. ”) disposed in a data path between the host control component and the one or more socketed memory modules, data-buffer control signals that correspond to the memory-module control signals and enable data transfer between the host control component and the one or more socketed memory modules.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 26, 27, 35 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Carlough et al (US 20190163384 A1) in view of Helmick et al (US 10679722 B2).
Regarding Claim 26, Carlough teaches the limitations of claim 25. Carlough further teaches wherein the control interface to receive the memory-module control signals (para 8 “In one embodiment a memory system for storing data in response to commands received from a Host is disclosed, the memory system comprising a memory control circuit to receive commands from the Host and to output command and control signals, at least one and preferably a plurality of memory devices configured to store data and receive command signals from the memory control circuit,”)
However, Carlough fails to teach that interface comprises receiver circuits to receive chip-select signals and command/address signals synchronously with respect to a first clock signal, and wherein the memory-module interface to re-transmit the memory module control signals comprises signal driver circuits to transmit the chip-select signals and the command/address signals to the one or more socketed memory modules synchronously with respect to a second clock signal.
Helmick teaches comprises receiver circuits (Fig. 23B: 2363) to receive chip-select signals (Fig. 23B: CS_n) and command/address signals (Fig. 23B: CMD+ADDRESS From Host) synchronously with respect to a first clock signal (Fig. 23B: Clk), and wherein the memory-module interface to re-transmit the memory module control signals (Fig. 23B: Cmd/ADDR Redistribution) comprises signal driver circuits (Fig. 23B: 2365) to transmit the chip-select signals and the command/address signals to the one or more socketed memory modules synchronously with respect to a second clock signal (Fig: 23B: Clk, 2366).
Helmick teaches specific circuitry that can perform the functions described by Carlough. These components and signals are well known in the art the schematic drawings of Helmick illustrate this fact.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Helmick to the teachings of Carlough to produce a memory module interface that receives and retransmits chip select signals and command/address signals synchronously with a second clock signal.
Regarding Claim 27, Carlough and Helmick teach the limitations of claim 26. Helmick further teaches comprising clock tree circuitry (Fig. 23B: 2366) to generate the second clock signal in response to the first clock signal (Fig. 23B: Clk), and wherein the memory-module interface comprises clock transmitter circuitry (Fig. 23B: 2368) to transmit the second clock signal (Fig. 23B: a plurality of Clocks for Redistribution To DRAM) to the one or more socketed memory modules.
Regarding Claim 35, this claim is rejected for the same reasons as claim 26.
Regarding Claim 36, this claim is rejected for the same reasons as claim 27.
Allowable Subject Matter
Claims 24, 30, 34, and 39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 24 and 34 are allowable for teaching that the data buffer controller ICs are not electrically connected to the data path between the host and memory modules. Carlough fails to teach this limitation. Therefore, these claims would be allowable if written in independent form.
Claims 30 and 39 are allowable for teaching a first and second buffer communication interface that allows the data buffer control module used to transmit first and second buffer control signals from the control buffer IC to the data buffers. Carlough is silent with respect to the number of data buffer communication interfaces are part of the control buffer IC. Therefore, these claims would be allowable if written in independent form.
Conclusion
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights