DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 26, 29-36, and 39-45 have been amended.
Claims 26-45 have been examined.
The drawing objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 26, 27, 29-33, 36, 37, and 39-43 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim corresponding claims of U.S. Patent No. 12,210,876. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 26-45 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2003/0225998 by Khan et al. (previously cited and hereinafter referred to as “Khan”) in view of US Publication No. 2018/0157490 by Craske (previously cited and hereinafter referred to as “Craske”).
Regarding claims 26 and 36, taking claim 26 as representative, Khan discloses:
a method comprising: receiving…an instruction of an instruction set (Khan discloses, at ¶ [0108] decoding and processing instructions, which discloses receiving an instruction of an instruction set.),
wherein the instructions in the instruction set include at least an opcode including first bits; and an offset including second bits, wherein the opcode specifies an operation to be performed (Khan discloses, at Figure 2 and related description, instructions having opcodes to specify the function of the instructions. See also ¶¶ [0134]-[0142], which disclose the instructions include bits for immediate offsets.), and
wherein a number of the second bits for the offset specified in each instruction is variable depending on whether the opcode of the instruction also implicitly identifies a base register as an operand of the operation or whether the instruction further includes third bits that explicitly identify the operand of the operation (Khan discloses, at ¶¶ [0134]-[0142], the number of offset bits varies. When the base is the PC or GP, more offset bits are available as these instructions implicitly specify the base register. See, e.g., ¶ [0212].);
determining…whether the base register is implicitly identified as the operand of the operation by the opcode in the received instruction (Khan discloses, at ¶ [0212], instructions that relatively address from implicitly specified base registers, which discloses determining whether the base register is implicitly identified by the opcode.); and
when the base register is implicitly identified as the operand of the operation by the opcode in the received instruction, outputting, by the decode unit, one or more control signals that cause an execution unit coupled to the decode unit to perform the operation specified by the opcode of the received instruction using the base register as the operand (Khan discloses, at ¶ [0108] decoding and processing instructions, which discloses, when the instruction implicitly identifies a base register as disclosed at ¶ [0212], output, by the decode unit, one or more control signals that cause an execution unit coupled to the decode unit to perform the operation specified by the opcode of the received instruction using the base register as the operand.).
Khan does not explicitly disclose the aforementioned receiving is at a decode unit and the aforementioned determining is by the decode unit.
However, in the same field of endeavor (e.g., processing systems) Craske discloses:
receiving and decoding instructions having various lengths (Craske discloses, at ¶ [0027], decoding and executing both 16-bit instructions and 32-bit instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Khan to include Craske’s decoding in order to improve performance by eliminating the need to translate variable length instructions to a single size.
Regarding claims 27 and 37, taking claim 27 as representative, Khan discloses the elements of claim 26, as discussed above. Khan also discloses:
the base register comprises a GP register (Khan discloses, at Table 8, instructions that implicitly identify the GP register, e.g., 0x0D.).
Regarding claims 28 and 38, taking claim 28 as representative, Khan discloses the elements of claim 26, as discussed above. Khan also discloses:
the base register comprises a PC register (Khan discloses, at Table 8, instructions that implicitly identify the PC register, e.g., 0x0C.).
Regarding claims 29 and 39, taking claim 29 as representative, Khan discloses the elements of claim 26, as discussed above. Khan also discloses:
the received instruction comprises a load instruction (Khan discloses, at Table 8, load instructions that implicitly identify the base register, e.g., 0x0D.).
Regarding claims 30 and 40, taking claim 30 as representative, Khan discloses the elements of claim 26, as discussed above. Khan also discloses:
the received instruction comprises a store instruction (Khan discloses, at Table 8, store instructions that implicitly identify the base register, e.g., 0x0D.).
Regarding claims 31 and 41, taking claim 31 as representative, Khan discloses the elements of claim 26, as discussed above. Khan does not explicitly disclose the received instruction comprises an add instruction. However, Khan discloses, at Table 7, add instructions. It would have been obvious to modify Khan’s add instruction to implicitly specify a base register in order to facilitate efficient instruction code.
Regarding claims 32 and 43, taking claim 32 as representative, Khan discloses the elements of claim 26, as discussed above. Khan also discloses:
the received instruction comprises a memory access instruction (Khan discloses, at Table 8, memory access instructions that implicitly identify the base register, e.g., 0x0D.).
Regarding claims 33 and 42, taking claim 33 as representative, Khan discloses the elements of claim 26, as discussed above. Khan does not explicitly disclose the instruction set comprises at least two load instructions having different bit lengths. However, Khan discloses, at Table 8, load instructions having different bit lengths, e.g., 0x11 and 0x12. It would have been obvious to modify Khan’s load instructions to implicitly specify a base register in order to facilitate efficient instruction code.
Regarding claims 34 and 44, taking claim 34 as representative, Khan discloses the elements of claim 26, as discussed above. Khan also discloses:
wherein the base registers include GP and PC registers and wherein the method further comprises determining … whether the opcode of the received instruction implicitly identifies a GP register as the operand (Khan discloses, at ¶¶ [0134]-[0142], instructions that include GP and PC base registers. As disclosed at ¶ [0142] and ¶ [0212], these registers can be implicitly identified. Executing these instructions involves determining which register is identified.); and
… determining … whether the received instruction implicitly identifies a PC register as the operand (Khan discloses, at ¶ [0108] decoding and processing instructions, which discloses, when the instruction implicitly identifies a base register as disclosed at ¶ [0212], determining which register is identified.).
Khan does not explicitly disclose that the aforementioned determining is by the decode unit and the aforementioned determination regarding the PC register is in response to a determination that the opcode of the received instruction does not implicitly identify a GP register as a base register.
However, in the same field of endeavor (e.g., processing systems) Craske discloses:
receiving and decoding instructions having various lengths (Craske discloses, at ¶ [0027], decoding and executing both 16-bit instructions and 32-bit instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Khan to include Craske’s decoding in order to improve performance by eliminating the need to translate variable length instructions to a single size.
Also, Kraske discloses decoding instructions. The particular order in which the determinations are made represents an obvious design choice. It would have been obvious to a person having ordinary skill in the art to base the second determination on the first, in either order, as circumstances determined.
Regarding claims 35 and 45, taking claim 35 as representative, Khan discloses the elements of claim 34, as discussed above. Khan also discloses:
receiving… a second instruction; and in response to a determination … that the second instruction does not implicitly identify a base register as the operand and instead explicitly identifies the operand, then outputting, by the decode unit, one or more control signals that cause the execution unit to perform an operation specified by the second instruction using the operand explicitly identified by the second instruction (Khan discloses, at ¶ [0108] decoding and processing instructions, which discloses, when the instruction explicitly specifies the operand, as disclosed at ¶ [0135], receiving, at the decode unit, a second instruction; and in response to a determination by the decode unit that the second instruction does not implicitly identify a GP register or a PC register as a base register, then outputting, by the decode unit, one or more control signals that cause the execution unit to perform an operation specified by the second instruction using an operand explicitly identified by the second instruction.).
Khan does not explicitly disclose the aforementioned receiving is at a decode unit and the aforementioned determining is by the decode unit.
However, in the same field of endeavor (e.g., processing systems) Craske discloses:
receiving and decoding instructions having various lengths (Craske discloses, at ¶ [0027], decoding and executing both 16-bit instructions and 32-bit instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Khan to include Craske’s decoding in order to improve performance by eliminating the need to translate variable length instructions to a single size.
Response to Arguments
On pages 10-11 of the response filed April 17, 2026 (“response”), the Applicant argues, “since the Applicant is currently in the process of making amendments to the claims of the present application in order to overcome various rejections and since such amendments may result in the claims of the present application being patentably distinct from the claims of the cited patent, Applicant has elected to refrain from filing a Terminal Disclaimer at this time. If, during prosecution, all other rejections are overcome and the claims of the present application are still considered unpatentable over the claims of the cited patent, Applicant will consider filing a Terminal Disclaimer to overcome any remaining non-statutory double-patenting rejections. Therefore, until that time, Applicant respectfully asks the Examiner to hold the non-statutory double patenting rejections in abeyance.”
The request to hold the double patenting rejection in abeyance is improper. MPEP § 804.1(B)(1) states, “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance…. Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only compliance with objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner.” In the interest of compact prosecution, the Examiner will consider the Applicant’s reply as adequate, rather than requiring a complete reply at this point.
On 13-14 of the response, the Applicant argues, “Khan discloses that encoding for 16-bit LDs (which relatively address from a stack pointer or global pointer) is implicit in the instruction. Khan further clarifies that this simply means encoding has to be translated to conform to the encoding specified in the 32-bit ISA. Khan does not disclose implicit identification of a base register. Furthermore, Khan does not disclose instructions in an instruction set where "each instruction in the instruction set includes at least: an opcode including first bits; and an offset including second bits" or where the "number of the second bits in each instruction is variable depending on whether the opcode also implicitly identifies a base register as an operand of the operation or whether the instruction further includes third bits that explicitly identify the operand of the operation." Thus, Applicant submits that Khan also does not disclose "determining, by the decode unit, whether the base register is implicitly identified as the operand of the operation by the opcode in the received instruction" or "when the base register is implicitly identified as the operand of the operation by the opcode in the received instruction, outputting, by the decode unit, one or more control signals that cause an execution unit coupled to the decode unit to perform the operation specified by the opcode of the received instruction using the base register as the operand."”
Though fully considered, the Examiner respectfully disagrees. Khan explicitly discloses, at ¶ [0212], implicit encoding of base registers in 16-bit instructions. Khan discloses translating at least some of the 16-bit instructions to 32-bit instructions. Whether this translation includes making the implicit specification of the base register explicit is debatable. The Examiner maintains that the reasons to make the specification of base register implicit in the first place, i.e., freeing up more bits to use for other purposes, e.g., offsets, still exist in the 32-bit format. That is, why wouldn’t the base register specification still be implicit even in the 32-bit instruction.
However, in order to expedite prosecution, the Examiner has set forth new grounds of rejection. Craske is cited as explicitly teaching decoding and executing both 16-bit and 32-bit instructions. See, e.g., ¶ [0027]. Doing so enables improved performance by omitting the conversion step disclosed by Khan. When combined with Khan’s disclosure of instructions that implicitly specify base registers, the combination discloses all elements of Applicant’s claims.
As discussed above, the other features argued by the Applicant, such as the instruction format and variable number of offset bits are taught by Khan. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 14 of the response the Applicant argues the remaining claims are patentable for similar reasons.
Though fully considered, the Examiner respectfully disagrees. The reasons set forth in the remarks and rejections presented above, including those regarding the independent claims, are applicable to these claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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