Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant's arguments filed June 11th, 2026, with respect to the independent claim rejections have been fully considered but they are not persuasive.
Applicant first argues that Tomei and Arelakis fail to teach the limitations of claim 1, as “the metadata described by Tomei is set simply to record an outcome of the compression attempt”, and “[n]either of the requests R nor R’ are generated by the Prefetch Buffer described by Arelakis”.
In response to the above arguments, Examiner respectfully disagrees. The argument regarding Tomei’s disclosure of metadata is not considered persuasive as there is no description of what the claimed “metadata” entails or describes in the language of claim 1. Claim 1 merely requires that the metadata is “associated with [a] memory request” and included in the memory request packet. This is consistent with the disclosure of Tomei, which describes metadata associated with a cache read request that is generated by a memory controller of a processing core. Applicant’s argument regarding Arelakis is also not considered persuasive as the “prefetch buffer” of Arelakis is not considered to be the entirety of the “hardware prefetcher” as required by the language of claim 1. One of ordinary skill in the art would understand that while a buffer may be included as part of a hardware prefetching component, a single buffer is not reasonably considered to perform all the functions of a prefetcher, which is a routine and conventional component of the microprocessor art. Arelakis discloses an entire control unit (Fig 28, [0157], data selection control unit 2890) which includes the prefetch buffer, and is responsible for accessing requested data and handling compression of said data. As claim 1 merely requires that the hardware prefetcher generates the claimed memory request, the disclosure of Arelakis is consistent with the language of the claims and the arguments are not considered persuasive.
The rest of Applicant’s arguments are based on the arguments addressed above, or are directed toward limitations of the claims added via amendment, and thus will be addressed in the updated rejections below. The above responses are applicable to arguments regarding dependent claims based on the arguments addressed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-7, 9-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tomei et al (US 2020/0210343, herein Tomei) in view of Arelakis (US 2022/0012184, herein Arelakis).
Regarding claim 1, Tomei teaches a computing device comprising:
a cache ([0023], cache memories);
generate a memory request, metadata associated with the memory request, and a memory request packet including the memory request and the metadata ([0042-0048], memory operations performed by compression-decompression functional block that update metadata associated with the requested data, [0040], [0044-0045], memory requests to provide data to caches);
a memory controller ([0023-0024], [0027], cache & memory control circuits, cache controller) configured to communicate a data packet to a hardware compression engine ([0036], [0038], compression-decompression functional block) responsive to execution of the memory request, the data packet including the metadata and data retrieved from a physical memory ([0042-0048], data requests between memory and cache layers involving metadata regarding compression); and
the hardware compression engine configured to receive the data packet and control communication of the data based on a compressibility of the data ([0035], [0062], evaluating if data is compressible).
Tomei fails to teach the device comprising a hardware prefetcher associated with the cache or wherein the compression engine communicates the data through an interconnect architecture.
Arelakis teaches a computing device comprising a cache ([0079], cache memories) and a hardware prefetcher associated with the cache ([0157], [0194], prefetch buffer to buffer prefetched data arriving based on a memory request), wherein a compression engine communicates data through an interconnect architecture ([0079], interconnection network) based on a compressibility of the data ([0005], [0134], [0176], issuing memory requests according to prefetch buffer utilization and data compressibility).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tomei and Arelakis to utilize prefetching and interconnections. While Tomei does not explicitly teach that the exemplary processor may utilize prefetching or an explicit interconnect between the cache levels and additional segments of memory, one of ordinary skill in the art would understand that both prefetching and interconnections between memories are routine and conventional aspects of the microprocessor art. As both Tomei and Arelakis disclose techniques for handling the compression of data in multilayer caches, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Tomei and Arelakis teaches the computing device of claim 1, wherein the hardware compression engine is further configured to: compress the data responsive to detecting that a condition of the metadata has been satisfied; and bypass compression of the data responsive to detecting that the condition has not been satisfied (Tomei [0035], [0062], evaluate if data can be compressed or if compression should be bypassed, [0025], [0042], [0048], bypass heavyweight compression for lightweight based on metadata conditions).
Regarding claim 3, the combination of Tomei and Arelakis teaches the computing device of claim 2, wherein the hardware compression engine is configured to bypass compression of the data by communicating the data through the interconnect architecture to the cache associated with the hardware prefetcher without compressing the data (Tomei [0035], skip compression if data is not compressible, Arelakis [0079], interconnection network).
Regarding claim 4, the combination of Tomei and Arelakis teaches the computing device of claim 2, wherein the hardware compression engine is configured to communicate the compressed data through the interconnect architecture to a decompression engine (Arelakis [0079], interconnect, [0081], decompressor unit & Tomei [0036], decompression functional block).
Regarding claim 5, the combination of Tomei and Arelakis teaches the computing device of claim 1, wherein the hardware prefetcher generates the metadata based on a request history associated with the hardware prefetcher, the request history describing prefetch memory requests promoted to demand memory requests, and the hardware prefetcher is configured to: compare a frequency of promotion of the prefetch memory requests to demand memory requests to a threshold frequency, the frequency of promotion based on the request history; and set a value of a compression indicator in the metadata based on a difference between the frequency and the threshold frequency (Arelakis [0157], prefetched requests of cache lines tracking hits and misses, [0170-0172], [0176], [0196], calculating prefetch buffer utilization to manage compression metadata and calculate a decision function for compression).
Regarding claim 6, the combination of Tomei and Arelakis teaches the computing device of claim 1, wherein the hardware compression engine is configured to compress the data based on the compressibility; and further comprising a decompression engine separated from the hardware compression engine by the interconnect architecture, the decompression engine configured to: receive the data compressed by the hardware compression engine; and decompress the data (Arelakis [0079], interconnect, [0081], decompressor unit & [0134], [0176], handling memory requests according to data compressibility).
Regarding claim 7, the combination of Tomei and Arelakis teaches the computing device of claim 6, wherein a compressibility history associated with the hardware prefetcher is updated based on an amount by which the data was compressed (Arelakis [0157], prefetched requests of cache lines tracking hit and miss history, [0170-0172], [0176], [0196], calculating prefetch buffer utilization to manage compression metadata and calculate a decision function for compression).
Regarding claim 9, the combination of Tomei and Arelakis teaches the computing device of claim 1, wherein the memory request is a prefetch memory request generated by the hardware prefetcher for the cache (Arelakis [0157], [0194], prefetch buffer to buffer prefetched data arriving based on a memory request).
Regarding claim 10, the combination of Tomei and Arelakis teaches the computing device of claim 1, wherein the compressibility of the data is based on historical compressibility data associated with memory requests from the hardware prefetcher (Arelakis [0157], prefetched requests of cache lines tracking hit and miss history, [0170-0172], [0176], [0196], calculating prefetch buffer utilization to manage compression metadata and calculate a decision function for compression).
Regarding claim 11, the combination of Tomei and Arelakis teaches the computing device of claim 1, wherein the hardware prefetcher generates the metadata based on an address of the physical memory associated with the memory request and specified by the memory request (Arelakis [0116], [0118], address translation utilizing metadata).
Regarding claim 12, Tomei teaches a system, comprising:
a cache (Fig 1, [0021], memory 104 & [0023], cache memories);
a memory controller in communication with the physical memory ([0023-0024], [0027], cache & memory control circuits, cache controller), the memory controller configured to receive memory requests and generate data packets, the data packets including data and metadata, the data retrieved from the physical memory based on the memory requests, and the metadata associated with the memory requests ([0042-0048], data requests between memory and cache layers involving metadata regarding compression); and
a compression engine in communication with the memory controller, ([0036], [0038], compression-decompression functional block), the compression engine configured to:
receive the data packets ([0042-0048], memory operations performed by compression-decompression functional block that update metadata associated with the requested data, [0040], [0044-0045], memory requests to provide data to caches);
determine a compressibility of the data included by the data packets based on the metadata included by the data packets ([0035], [0062], determine if data is compressible); and
control communication of the data packets based on the compressibility of the data included by the data packets ([0035], [0062], compression of a first or second type according to data compressibility).
Tomei fails to teach the wherein the compression engine communicates the data through an interconnect architecture.
Arelakis teaches a system comprising a memory ([0079], cache memories), wherein a compression engine communicates data through an interconnect architecture ([0079], interconnection network) based on a compressibility of the data ([0005], [0134], [0176], issuing memory requests according to prefetch buffer utilization and data compressibility).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tomei and Arelakis to utilize prefetching and interconnections. While Tomei does not explicitly teach that the exemplary processor may utilize prefetching or an explicit interconnect between the cache levels and additional segments of memory, one of ordinary skill in the art would understand that both prefetching and interconnections between memories are routine and conventional aspects of the microprocessor art. As both Tomei and Arelakis disclose techniques for handling the compression of data in multilayer caches, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 13, the combination of Tomei and Arelakis teaches the system of claim 12, wherein a classification of each memory request is based on respective metadata associated with each memory request (Tomei [0042-0048], memory operations performed by compression-decompression functional block that update metadata associated with the requested data, [0040], [0044-0045], memory requests to provide data to caches), the classification being one of a prefetch classification or a demand classification, and the compressibility is based on the classification (Arelakis [0157], prefetched requests of cache lines tracking hit and miss history, [0170-0172], [0176], [0196], calculating prefetch buffer utilization to manage compression metadata and calculate a decision function for compression).
Claim 14 refers to a system embodiment of the device embodiment of claim 2. Therefore, the above rejection for claim 2 is applicable to claim 14.
Claims 16, 17, 18, and 20 refer to a method embodiment of the device embodiment of claims 1, 2, 5, and 7, respectively. Therefore, the above rejections for claims 1, 2, 5, and 7 are applicable to claims 16, 17, 18, and 20, respectively.
3. Claims 8, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tomei and Arelakis as applied to claims above, and further in view of Ichien (US 9,807,189).
Regarding claim 8, the combination of Tomei and Arelakis teaches the computing device of claim 1. Tomei and Arelakis fails to teach wherein the compressibility is based on a memory level parallelism (MLP) associated with the memory request and described by the metadata.
Ichien teaches a computing device wherein a compressibility of data is based on a memory level parallelism (MLP) associated with a memory request and described by metadata (10:1-33, 12:39-64, 13:59-14:4, perform compression process according to parallelism indicated by metadata variable P).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tomei and Arelakis with those of Ichien to account for a degree of parallelism in the data to be compressed. While all three references disclose performing compression operations in parallel (Tomei [0040], Arelakis [0157]), Tomei and Arelakis do not explicitly disclose evaluating data compressibility based on a degree of parallelism. However, as memory/data level parallelism is a routine and conventional concept in the microprocessor art, this combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Claim 15 refers to a system embodiment of the device embodiment of claim 8. Therefore, the above rejection for claim 8 is applicable to claim 15.
Claim 19 refers to a method embodiment of the device embodiment of claim 8. Therefore, the above rejection for claim 8 is applicable to claim 19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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