DETAILED ACTION
Claims 2-21 are pending. Claim 1 is cancelled.
Priority: 4/22/2009(provisional)
Assignee: Rambus
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 10,510,395. The following table(s) show sufficiently that the corresponding claims are obvious variants of each other. See MPEP 804(II)(B).
18/991,946
(Instant)
2. A memory controller integrated circuit, comprising: an interface to couple the memory controller integrated circuit, via a conductive link, to a dynamic random access memory (DRAM) device having banks, including a first bank and a second bank; and logic to, via the interface, issue data access commands to the DRAM device, wherein the data access commands include commands addressed to a first one of the banks and commands addressed to a second one of the banks; wherein the logic is to sequence the issuance of the commands addressed to the second one of the banks, relative to issuance of the commands addressed to the first one of the banks, in a manner dependent on progress information, received from the DRAM device, indicating that the first one of the banks is undergoing a refresh operation.
10. A memory controller integrated circuit, comprising: a first interface to couple the memory controller integrated circuit, via a first conductive link, to a first set of banks of a dynamic random access memory (DRAM) device; a second interface to couple the memory controller integrated circuit, via a second conductive link, to a second set of banks of the DRAM device; logic to place the DRAM device into a selective one of a normal data transmission mode, in which the DRAM device is operable to transfer data between the first set of banks and the memory controller integrated circuit at a first data rate, and a low power mode, in which the DRAM device is disabled from transferring data between the first set of banks and the memory controller integrated circuit at the first data rate; and logic to, via the first interface, issue data access commands to first set of banks of the DRAM device, and via the second interface, issue data access commands to the second set of banks of the DRAM device, wherein the data access commands issued to the first set of banks include commands addressed to a first bank and wherein the data access commands issued to the second set of banks include commands addressed to a second bank; logic is to sequence the issuance of the commands addressed to the second bank, relative to issuance of the commands addressed to the first bank, in a manner dependent on progress information, received from the DRAM device, indicating that the first bank is undergoing a refresh operation in association with the low power mode.
Both are similar to claim 15.
10,510,395
(Parent)
1. A memory controller integrated circuit (IC) to control a dynamic random access memory (DRAM) device, the memory controller IC comprising:
interface circuitry to command the DRAM device to perform a refresh operation on a selected bank of the DRAM device;
wherein the memory controller IC is to observe a first time interval from completion of the refresh operation on the selected bank before sending a command directed to the selected bank via the interface circuitry; and
wherein the interface circuitry is to issue a command directed to a bank of the DRAM device other than the selected bank using a second time interval from completion of the refresh operation on the selected bank, the second time interval being shorter than the first time interval.
7. The memory controller IC of claim 1, wherein the memory controller IC further has logic to receive from the DRAM device information identifying whether a refresh operation is in progress on the memory device.
Similar to method claim 10.
Similar to method claim 15.
Analysis
Claim(s) 2, 10 and 15 of the instant claims derive support from 0026, 0011, 0012, 0013; This means that sequencing issuance of commands based on progress information is an obvious modification to the parent claims. Claim 2 merely recites the informational mechanism used to implement the bank dependent command sequencing already protected by patented claims 1 and 7.
18/991,946
(Instant)
3 . The memory controller integrated circuit of claim 2, wherein:
a period is to expire following receipt of the progress information and prior to transmission of an ensuing self-refresh command, the period being at least
a first time interval when the selected one is the first one of the banks; and
a second time interval when the selected one is the second one of the banks; and
wherein the first time interval is greater than the second time interval.
Similar to system claim 11.
Similar to method claim 16.
10,510,395
(Parent)
1.
“…wherein the memory controller IC is to observe a first time interval from completion of the refresh operation on the selected bank before sending a command directed to the selected bank via the interface circuitry; and
wherein the interface circuitry is to issue a command directed to a bank of the DRAM device other than the selected bank using a second time interval from completion of the refresh operation on the selected bank, the second time interval being shorter than the first time interval…”
Analysis
The spec in 0011-0013, 0026 and Fig. 6 teaches progress information is what enables implementation of timing distinction. Claim merely claims an obvious implementation of patent claim 1.
18/991,946
(Instant)
4 . The memory controller integrated circuit of claim 2, wherein the refresh operation is a self-refresh operation and wherein the memory controller integrated circuit further comprises logic operable to specify to the DRAM device in association with the self-refresh operation a selective incrementing order to be applied in performing the self-refresh operation.
Similar to system claim 12.
Similar to method claim 17.
10,510,395
(Parent)
6. The memory controller IC of claim 1, wherein further, the memory controller IC is to explicitly command the DRAM device to perform the refresh operation on a basis that is a selective one of a refresh operation where the DRAM device progresses incrementally through row addresses of the selected bank, or a refresh operation where the DRAM device progresses incrementally through all banks for a given row address before proceeding to a next row address.
Similar to method claim 15.
Analysis
The specification discloses in [0024], which are bank and row implementation detail of the same refresh protocol. Therefore claim 4 combines claim 2 sequencing concepts and patent claim 6 ordering concepts.
18/991,946
(Instant)
5 . The memory controller integrated circuit of claim 2, wherein the conductive link is a differential link, and wherein the memory controller integrated circuit further comprises a serializer, the data access commands being issued to the DRAM device as differential, serialized information.
Similar to system claim 13.
Similar to method claim 18.
10,510,395
(Parent)
Claim(s) 1, 10, 19
Analysis
The specification 0021 and Fig. 4a, among others describes serialized differential interfaces between controller and DRAM. The claimed serializer merely implements the communication architecture used by the patented refresh protocol. The serializer contributes no patentably distinct refresh-control concept relative to patent claim 1.
18/991,946
(Instant)
6 . The memory controller integrated circuit of claim 2, wherein the banks are a first group of banks, wherein the DRAM device comprises a second group of banks, and wherein the memory controller integrated circuit further comprises logic operable to selectively place a first one of the first set of banks and the second set of banks into a low power mode, in which the calibrated data transfer between the memory controller integrated circuit and the respective first set of banks or second set of banks is disabled, and wherein the memory controller integrated circuit further comprises logic to transmit a refresh command, to the DRAM device, the refresh commands being directed to a second one of the first set of banks or the second set of banks during the low power mode.
Similar to method claim 19.
10,510,395
(Parent)
2. The memory controller IC of claim 1, wherein: the interface circuitry is to exchange the commands with the DRAM device via calibrated links, each calibrated link operating at a first data rate; in a low power state, the DRAM device is to disable exchange of commands with the interface circuitry at the first data rate; and in the low power state, the DRAM device is to perform a self-refresh operation.
Similar to system claim 11.
Analysis
The spec in [0014], [0024], describes the low power state, refresh signal during low power operation. Claim 6 merely applies the patented refresh-control scheme to multiple bank groups.
18/991,946
(Instant)
7. The memory controller integrated circuit of claim 6, wherein:
the interface is a first interface, and is to couple the memory controller integrated circuit to the DRAM device to issue commands to the first set of banks, the conductive link being a first conductive link;
the memory controller integrated circuit further comprises a second interface to couple the memory controller integrated circuit, via a second conductive link, to the DRAM device, to issue commands to the second set of banks.
Similar to method claim 20.
10,510,395
(Parent)
Claim(s) 1, 10, 19
Analysis
The spec shows the interfaces, controllers and bank groups in Fig. 3 and [0017]. Claim 7 simply mirrors the architecture already disclosed as the implementation environment of the patented invention. No new refresh principle is introduced.
18/991,946
(Instant)
8 . The memory controller integrated circuit of claim 6, wherein the memory controller integrated circuit further comprises logic operable to transmit, to the DRAM device, auto-refresh commands which are respective to each of the first set of banks and the second set of banks.
Similar to system claim 14.
Similar to method claim 20.
10,510,395
(Parent)
Claim(s) 1, 10, 19
Analysis
Patent claim 1 already covers controller-directed refreshes to selected banks. The spec discusses controller-controlled refresh operations for different bank sets. Using separate auto-refresh commands for different bank groups is an obvious extension pf the patented bank specific refresh protocol.
18/991,946
(Instant)
9 . The memory controller integrated circuit of claim 2, wherein:
the interface is a command interface;
the memory controller integrated circuit further comprises a data interface, the data interface operable to transfer data with the DRAM device at a first data rate;
the memory controller integrated circuit further comprises logic to place the DRAM device into a selective one of a normal data transmission mode, in which the DRAM device is operable to transfer data with the memory controller integrated circuit at the first data rate, and a low power mode, in which the DRAM device is disabled from transferring data with the memory controller integrated circuit at the first data rate; and
the memory controller integrated circuit further comprises logic operable to transmit, to the DRAM device, in association with the low power mode, a command for the DRAM device to perform a refresh operation.
Similar to method claim 21.
10,510,395
(Parent)
2. The memory controller IC of claim 1, wherein: the interface circuitry is to exchange the commands with the DRAM device via calibrated links, each calibrated link operating at a first data rate; in a low power state, the DRAM device is to disable exchange of commands with the interface circuitry at the first data rate; and in the low power state, the DRAM device is to perform a self-refresh operation.
3. The memory controller IC of claim 2, wherein: the interface circuitry is further to supply a clock signal to the DRAM device, and to freeze the clock signal when the DRAM device is in the low power state; and the memory controller IC is further to selectively communicate one or more commands to the DRAM device when the DRAM device is in the low power state in a manner that exchanges data with the DRAM device at a data rate that is slower than the first data rate.
Analysis
Patented claims 2-3 already recite calibrated command links low power mode, self-refresh, and disabling. The spec in [0014]-[0015], [0024] describes this transition between normal operation and low power refresh operations. Claim(s) 9 and 21 simply restates the same refresh-control framework using slightly different interface terminology.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 3, 11, 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 3, 11, 16 the following limitations are unsupported by the specification:
memory controller integrated circuit, wherein: a period is to expire following receipt of the progress information and prior to transmission of an ensuing self-refresh command, the period being at least a first time interval when the selected one is the first one of the banks; and a second time interval when the selected one is the second one of the banks; and wherein the first time interval is greater than the second time interval.
Paras. 0012, 0013, 0024, 0025 contain subject matter related to timing, delays and intervals, but the elements of the claims are unsupported. It is not clear where in the spec is the inventor shown to possess the concept that the waiting period after receiving progress information depends on which bank is selected, and that one bank requires a longer minimum interval than another. The interpretation of refresh duration between banks is the interpretation for prior art purposes.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 4-10, 12-15, 17-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware et al.(2008/0028127), and further in view of Remaklus et al.(2005/0265103).
As per claim 2, Ware discloses:
A memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.]), comprising:
an interface to couple the memory controller integrated circuit, via a conductive link, to a dynamic random access memory (DRAM) device having banks, including a first bank and a second bank(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]);
and logic to, via the interface, issue data access commands to the DRAM device, wherein the data access commands include commands addressed to a first one of the banks and commands addressed to a second one of the banks(Ware, [0026 -- For purposes of example, the memory devices 207 may be synchronous double-data rate (DDR) DRAM devices that respond to commands and addresses received at CA interface 214, by outputting read and receiving write data via data interface 212]);
Ware does not explicitly disclose the following, however Remaklus discloses:
wherein the logic is to sequence the issuance of the commands addressed to the second one of the banks, relative to issuance of the commands addressed to the first one of the banks(Remaklus, [0011 -- This method allows the memory controller to refresh a particular memory bank while permitting other memory banks to remain open for access, resulting in higher performance; reads and writes to other banks can generally continue in parallel and uninterrupted.], [0034 -- Since the memory controller 120 does not know when this last bank was refreshed, the memory controller 120 directs the volatile memory 110 to perform an auto-refresh operation on the next bank, BankY+1, that is due for refresh as soon as practicable.], [0035 -- Hence, after the volatile memory 110 exits the self-refresh mode, information relating to the bank address and the row address of the last refreshed row and bank is available to the memory controller 120 from the exit row address latch 230 and the exit bank address latch 220. The memory controller 120 can then utilize this information for future operations accordingly.]), in a manner dependent on progress information, received from the DRAM device(Remaklus, [0034 -- The memory controller 120 retrieves the content of the exit bank address latch 220 and then uses it to identify the last bank that the volatile memory 110 refreshed prior to exiting self-refresh mode.]), indicating that the first one of the banks is undergoing a refresh operation(Remaklus, [0010 -- During periods of non-use, the memory controller may place the memory in the self-refresh mode. In the self-refresh mode, the memory uses its own internal clock and refresh address counter to generate refreshes to refresh the row(s) of the memory. This method is good for saving power during idle states since the self-refresh mode can be used.], [0034 -- Since the memory controller 120 does not know when this last bank was refreshed, the memory controller 120 directs the volatile memory 110 to perform an auto-refresh operation on the next bank, BankY+1, that is due for refresh as soon as practicable.], [0040 -- The bank address 470 is used to select one of the banks 410 for refresh. Because the memory controller 120 (see FIG. 1) is aware of the specific bank to be refreshed, access to the other internal banks may continue without interruption.], [0040 -- The bank address 470 is used to select one of the banks 410 for refresh. Because the memory controller 120 (see FIG. 1) is aware of the specific bank to be refreshed, access to the other internal banks may continue without interruption.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 4, the rejection of claim 2 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit;
Ware does not explicitly disclose the following, however Remaklus discloses:
memory controller integrated circuit(Remaklus, [0032 -- FIG. 1 shows an arrangement 100 that can be used to practice the seamless refresh method.]), wherein the refresh operation is a self-refresh operation and wherein the memory controller integrated circuit further comprises logic operable to specify to the DRAM device in association with the self-refresh operation a selective incrementing order to be applied in performing the self-refresh operation(Remaklus, [0060 -- Furthermore, during each self-refresh operation, the entry bank address latch 210 is incremented by the refresh trigger 530. By incrementing the entry bank address latch 210, the bank address is updated to identify the next target bank to be refreshed.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 5, the rejection of claim 2 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.]);
wherein the conductive link is a differential link(Ware, [0041 -- Following the timing and path-width examples described in reference to FIGS. 3-5, each high-speed serial interface 402 may include a single-link, differential signal receiver to sample an incoming serial data signal at 2 Gb/s.]), and wherein the memory controller integrated circuit further comprises a serializer, the data access commands being issued to the DRAM device as differential, serialized information(Ware, [0041 -- Data buffer 400 includes four conversion circuits 401.sub.1-401.sub.4, each having a high-speed serial interface 402 to support serialized read and write data transfer to/from a respective memory access requester (e.g., a respective one of four CPUs 201A-201D in FIG. 3), and a lower-speed parallel-I/O memory interface 432 to support parallel read and write data transfer to/from a respective one of memory devices W-Z (e.g., memory devices 207W-207Z in FIG. 3).]).
As per claim 6, the rejection of claim 2 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit;
Ware does not explicitly disclose the following, however Remaklus discloses:
a memory controller integrated circuit(Remaklus, [0032 -- FIG. 1 shows an arrangement 100 that can be used to practice the seamless refresh method.]);
wherein the banks are a first group of banks, wherein the DRAM device comprises a second group of banks, and wherein the memory controller integrated circuit further comprises logic operable to selectively place a first one of the first set of banks and the second set of banks into a low power mode, in which the calibrated data transfer between the memory controller integrated circuit and the respective first set of banks or second set of banks is disabled(Remaklus, [0012 -- In one embodiment, a seamless refresh method is provided which allows a specific bank to be identified for the first self-refresh operation upon a memory entering self-refresh mode; the refresh method also allows information relating to the last refreshed bank to be conveyed to a memory controller upon the memory exiting self-refresh mode.], [0032 -- In one embodiment, a seamless refresh method is provided which allows a specific bank to be identified for the first self-refresh operation upon a memory entering self-refresh mode; the refresh method also allows information relating to the last refreshed bank to be conveyed to a memory controller upon the memory exiting self-refresh mode.]), and wherein the memory controller integrated circuit further comprises logic to transmit a refresh command, to the DRAM device, the refresh commands being directed to a second one of the first set of banks or the second set of banks during the low power mode(Remaklus, [0033 -- When the memory controller 120 commands the volatile memory 110 to enter self-refresh mode, the memory controller 120 signals to the volatile memory 110 which bank to refresh next by using a target bank address. The target bank address is loaded into the entry bank address latch 210.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 7, the rejection of claim 6 is incorporated, in addition, Ware discloses:
the interface is a first interface, and is to couple the memory controller integrated circuit to the DRAM device to issue commands to the first set of banks, the conductive link being a first conductive link(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]);
the memory controller integrated circuit further comprises a second interface to couple the memory controller integrated circuit, via a second conductive link, to the DRAM device, to issue commands to the second set of banks(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]).
As per claim 8, the rejection of claim 6 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit;
Ware does not explicitly disclose the following, however Remaklus discloses:
wherein the memory controller integrated circuit further comprises logic operable to transmit, to the DRAM device, auto-refresh commands which are respective to each of the first set of banks and the second set of banks(Remaklus, [0040 -- The memory controller 120 may direct the volatile memory 110 to auto-refresh a specific memory bank within the volatile memory 110 while other memory banks remain available for access. For each auto-refresh cycle initiated by the memory controller 120, the bank address 470 may be loaded by the memory controller 120 (see FIG. 1) into the entry bank address latch 210. The bank address 470 is used to select one of the banks 410 for refresh.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 9, the rejection of claim 2 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.]);
wherein: the interface is a command interface(Ware, [0026 -- Each memory device 207 may include a control logic circuit 211 having a data interface 212 and a command/address (CA) interface 214]);
the memory controller integrated circuit further comprises a data interface, the data interface operable to transfer data with the DRAM device at a first data rate(Ware, [0026 -- Each memory device 207 may include a control logic circuit 211 having a data interface 212 and a command/address (CA) interface 214, i.e. a transfer of data implies data rate]);
Ware does not explicitly disclose the following, however Remaklus discloses:
the memory controller integrated circuit further comprises logic to place the DRAM device into a selective one of a normal data transmission mode, in which the DRAM device is operable to transfer data with the memory controller integrated circuit at the first data rate(Remaklus, [0040 -- The memory controller 120 may direct the volatile memory 110 to auto-refresh a specific memory bank within the volatile memory 110 while other memory banks remain available for access. For each auto-refresh cycle initiated by the memory controller 120, the bank address 470 may be loaded by the memory controller 120 (see FIG. 1) into the entry bank address latch 210.]), and a low power mode, in which the DRAM device is disabled from transferring data with the memory controller integrated circuit at the first data rate(Remaklus, [0048 -- When the volatile memory 110 is commanded into self-refresh mode, the volatile memory 110 begins to generate refreshes internally using the bank address currently stored in the entry bank address latch 210 from the point where the memory controller 120 left off issuing the last auto-refresh command to the volatile memory 110.]);
and the memory controller integrated circuit further comprises logic operable to transmit, to the DRAM device, in association with the low power mode, a command for the DRAM device to perform a refresh operation(Remaklus, [0034 -- FIG. 3 shows that in Cycle "2" the memory controller 120 issues the command to place the volatile memory 110 in self-refresh mode indicating that the memory's first self-refresh cycle is to be performed on a specific bank, BankX. Then, at Cycle "m+1", the volatile memory 110 exits self-refresh mode and loads the bank address of the last refreshed bank, BankY, into the exit bank address latch 220.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 10, Ware discloses:
A memory controller integrated circuit, comprising:
a first interface to couple the memory controller integrated circuit, via a first conductive link, to a first set of banks of a dynamic random access memory (DRAM) device(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]);
a second interface to couple the memory controller integrated circuit, via a second conductive link, to a second set of banks of the DRAM device(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]);
Ware does not explicitly disclose the following, however Remaklus:
logic to place the DRAM device into a selective one of a normal data transmission mode, in which the DRAM device is operable to transfer data between the first set of banks and the memory controller integrated circuit at a first data rate(Remaklus, [0040 -- The memory controller 120 may direct the volatile memory 110 to auto-refresh a specific memory bank within the volatile memory 110 while other memory banks remain available for access. For each auto-refresh cycle initiated by the memory controller 120, the bank address 470 may be loaded by the memory controller 120 (see FIG. 1) into the entry bank address latch 210.]), and a low power mode, in which the DRAM device is disabled from transferring data between the first set of banks and the memory controller integrated circuit at the first data rate(Remaklus, [0048 -- When the volatile memory 110 is commanded into self-refresh mode, the volatile memory 110 begins to generate refreshes internally using the bank address currently stored in the entry bank address latch 210 from the point where the memory controller 120 left off issuing the last auto-refresh command to the volatile memory 110.]);
and logic to, via the first interface, issue data access commands to first set of banks of the DRAM device, and via the second interface, issue data access commands to the second set of banks of the DRAM device, wherein the data access commands issued to the first set of banks include commands addressed to a first bank and wherein the data access commands issued to the second set of banks include commands addressed to a second bank(Ware, [0021 -- In the particular embodiment of FIG. 1, each of the four memory devices 105W-105Z may include a memory core formed by four address-selectable memory banks 107P-107S (the banks being designated P, Q, R and S) and control logic 110 to store data within and retrieve data from the memory core in response to memory access commands.]);
Ware does not explicitly disclose the following, however Remaklus discloses:
logic Remaklus, [0034 -- Since the memory controller 120 does not know when this last bank was refreshed, the memory controller 120 directs the volatile memory 110 to perform an auto-refresh operation on the next bank, BankY+1, that is due for refresh as soon as practicable.], [0035 -- Hence, after the volatile memory 110 exits the self-refresh mode, information relating to the bank address and the row address of the last refreshed row and bank is available to the memory controller 120 from the exit row address latch 230 and the exit bank address latch 220. The memory controller 120 can then utilize this information for future operations accordingly.]), in a manner dependent on progress information, received from the DRAM device(Remaklus, [0034 -- The memory controller 120 retrieves the content of the exit bank address latch 220 and then uses it to identify the last bank that the volatile memory 110 refreshed prior to exiting self-refresh mode.]), indicating that the first bank is undergoing a refresh operation in association with the low power mode(Remaklus, [0010 -- During periods of non-use, the memory controller may place the memory in the self-refresh mode. In the self-refresh mode, the memory uses its own internal clock and refresh address counter to generate refreshes to refresh the row(s) of the memory. This method is good for saving power during idle states since the self-refresh mode can be used.], [0034 -- Since the memory controller 120 does not know when this last bank was refreshed, the memory controller 120 directs the volatile memory 110 to perform an auto-refresh operation on the next bank, BankY+1, that is due for refresh as soon as practicable.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 12, the rejection of claim 10 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit;
Ware does not explicitly disclose the following, however Remaklus discloses:
a memory controller integrated circuit(Remaklus, [0032 -- FIG. 1 shows an arrangement 100 that can be used to practice the seamless refresh method.]);
wherein the refresh operation is a self-refresh operation and wherein the memory controller integrated circuit further comprises logic operable to specify to the DRAM device in association with the self-refresh operation a selective incrementing order to be applied in performing the self-refresh operation(Remaklus, [0060 -- Furthermore, during each self-refresh operation, the entry bank address latch 210 is incremented by the refresh trigger 530. By incrementing the entry bank address latch 210, the bank address is updated to identify the next target bank to be refreshed.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 13, the rejection of claim 10 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.]);
wherein each conductive link is a differential link(Ware, [0041 -- Following the timing and path-width examples described in reference to FIGS. 3-5, each high-speed serial interface 402 may include a single-link, differential signal receiver to sample an incoming serial data signal at 2 Gb/s.]), and wherein the memory controller integrated circuit further comprises, for each of the first interface and the second interface, a serializer, the data access commands being issued to the DRAM device via the respective first interface or second interface as differential, serialized information(Ware, [0041 -- Data buffer 400 includes four conversion circuits 401.sub.1-401.sub.4, each having a high-speed serial interface 402 to support serialized read and write data transfer to/from a respective memory access requester (e.g., a respective one of four CPUs 201A-201D in FIG. 3), and a lower-speed parallel-I/O memory interface 432 to support parallel read and write data transfer to/from a respective one of memory devices W-Z (e.g., memory devices 207W-207Z in FIG. 3).]).
As per claim 14, the rejection of claim 10 is incorporated, in addition, Ware discloses:
a memory controller integrated circuit;
Ware does not explcitly disclose the following, however Remaklus discloses:
wherein the memory controller integrated circuit further comprises logic operable to transmit, to the DRAM device, auto-refresh commands which are respective to each of the first set of banks and the second set of banks(Remaklus, [0040 -- The memory controller 120 may direct the volatile memory 110 to auto-refresh a specific memory bank within the volatile memory 110 while other memory banks remain available for access. For each auto-refresh cycle initiated by the memory controller 120, the bank address 470 may be loaded by the memory controller 120 (see FIG. 1) into the entry bank address latch 210. The bank address 470 is used to select one of the banks 410 for refresh.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
As per claim 15, Ware discloses:
A method of operation in a memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.]), the memory controller integrated circuit having an interface to couple the memory controller integrated circuit, via a conductive link, to a dynamic random access memory (DRAM) device having banks, including a first bank and a second bank(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]), the method comprising, using logic of the memory controller integrated circuit:
issuing data access commands to the DRAM device, wherein the data access commands include commands addressed to a first one of the banks and commands addressed to a second one of the banks(Ware, [0026 -- For purposes of example, the memory devices 207 may be synchronous double-data rate (DDR) DRAM devices that respond to commands and addresses received at CA interface 214, by outputting read and receiving write data via data interface 212]);
Ware does not explicitly disclose the following, however Remaklus discloses:
and sequencing the issuance of the commands addressed to the second one of the banks, relative to issuance of the commands addressed to the first one of the banks(Remaklus, [0034 -- Since the memory controller 120 does not know when this last bank was refreshed, the memory controller 120 directs the volatile memory 110 to perform an auto-refresh operation on the next bank, BankY+1, that is due for refresh as soon as practicable.], [0035 -- Hence, after the volatile memory 110 exits the self-refresh mode, information relating to the bank address and the row address of the last refreshed row and bank is available to the memory controller 120 from the exit row address latch 230 and the exit bank address latch 220. The memory controller 120 can then utilize this information for future operations accordingly), in a manner dependent on progress information, received from the DRAM device(Remaklus, [0034 -- The memory controller 120 retrieves the content of the exit bank address latch 220 and then uses it to identify the last bank that the volatile memory 110 refreshed prior to exiting self-refresh mode.]), indicating that the first one of the banks is undergoing a refresh operation(Remaklus, [0010 -- During periods of non-use, the memory controller may place the memory in the self-refresh mode. In the self-refresh mode, the memory uses its own internal clock and refresh address counter to generate refreshes to refresh the row(s) of the memory. This method is good for saving power during idle states since the self-refresh mode can be used.], [0034 -- Since the memory controller 120 does not know when this last bank was refreshed, the memory controller 120 directs the volatile memory 110 to perform an auto-refresh operation on the next bank, BankY+1, that is due for refresh as soon as practicable.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
Claim(s) 17 is directed to method steps that implement the system claim 4, and therefore the corresponding mappings are incorporated.
Claim(s) 18 is directed to method steps that implement the system claim 5, and therefore the corresponding mappings are incorporated.
Claim(s) 19 is directed to method steps that implement the system claim 6, and therefore the corresponding mappings are incorporated.
As per claim 20, the rejection of claim 15 is incorporated, in addition, Ware discloses:
wherein the interface is a first interface which couples the memory controller integrated circuit to the DRAM device to issue commands to a first set of banks, the conductive link being a first conductive link(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]), wherein the memory controller integrated circuit further has a second interface which couples the memory controller integrated circuit, via a second conductive link, to the DRAM device to issue commands to the second set of banks(Ware, [0019 -- Each of the buffer devices 103 may include multiple control interfaces 115 (designated A-D) each coupled to a respective one of the requestors 101A-101D via an n-conductor signal path 102, and also multiple memory interfaces 117 each coupled to a respective one of the memory devices 105W-105Z via an m-conductor signaling path 104]),;
Ware does not explicitly disclose the following, however Remaklus discloses:
and wherein the method further comprises transmitting, to the DRAM device, auto-refresh commands which are respective to each of the first set of banks and the second set of banks(Remaklus, [0040 -- The memory controller 120 may direct the volatile memory 110 to auto-refresh a specific memory bank within the volatile memory 110 while other memory banks remain available for access. For each auto-refresh cycle initiated by the memory controller 120, the bank address 470 may be loaded by the memory controller 120 (see FIG. 1) into the entry bank address latch 210. The bank address 470 is used to select one of the banks 410 for refresh.]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Remaklus into the system of Ware for the benefit of providing seamless self-refresh for banks of volatile memories efficiently(Remaklus, [0014]).
Claim(s) 21 is directed to method steps that implement the system claim 9, and therefore the corresponding mappings are incorporated.
Claim(s) 3, 11, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware et al.(2008/0028127), in view of Remaklus et al.(2005/0265103), and further in view of Ware et al.(2006/0004955, “Perego”)
As per claim 3, the rejection of claim 2 is incorporated, in addition, Ware discloses:
A memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.])
Ware does not explicitly disclose the following, however Perego discloses:
memory controller integrated circuit(Perego, [0091 -- System 1000 includes a memory controller 1005 and a memory component 1010]), wherein: a period is to expire following receipt of the progress information and prior to transmission of an ensuing self-refresh command, the period being at least a first time interval when the selected one is the first one of the banks and a second time interval when the selected one is the second one of the banks; and wherein the first time interval is greater than the second time interval(Perego, [0108 -- Controller 1065 then refreshes rows 4 through 7 of banks 0 through 7, again in any order. This process continues until the last set of rows is refreshed. The time t.sub.REFROWSET allocated for refreshing each set of rows is approximately the t.sub.REF interval divided by the number of row sets. If, at the end of each t.sub.REFROWSET, there are rows of banks that had not been refreshed because the banks had been too heavily utilized by read and write transactions, then controller 1065 holds off subsequent data-access transactions until those banks had been refreshed. The row set size can vary from the minimum (one row of each bank) to the maximum (all rows of each bank).]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Perego into the system of Ware for the benefit of avoiding lost clock cycles and improves electronic system efficiency and performance characteristics, even when the commands are transmitted at different times. (Perego, [0199]).
As per claim 11, the rejection of claim 10 is incorporated, in addition, Ware discloses:
A memory controller integrated circuit(Ware, [0025 -- FIG. 3 illustrates a more specific embodiment of a cross-threaded memory system 200 in which buffer devices (205I-205L and 206) and memory devices 207W-207Z may be disposed within multi-chip-package memory subsystems 203.sub.1-203.sub.4.])
Ware does not disclose the following, however Perego discloses:
memory controller integrated circuit(Perego, [0091 -- System 1000 includes a memory controller 1005 and a memory component 1010]), wherein: a period is to expire following receipt of the progress information and prior to transmission of an ensuing self-refresh command, the period being at least a first time interval when the selected one is the first bank; and a second time interval when the selected one is the second bank and wherein the first time interval is greater than the second time interval(Perego, [0108 -- Controller 1065 then refreshes rows 4 through 7 of banks 0 through 7, again in any order. This process continues until the last set of rows is refreshed. The time t.sub.REFROWSET allocated for refreshing each set of rows is approximately the t.sub.REF interval divided by the number of row sets. If, at the end of each t.sub.REFROWSET, there are rows of banks that had not been refreshed because the banks had been too heavily utilized by read and write transactions, then controller 1065 holds off subsequent data-access transactions until those banks had been refreshed. The row set size can vary from the minimum (one row of each bank) to the maximum (all rows of each bank).]).
Therefore it would have been obvious to a person of ordinary skill at the time of invention to incorporate the features of Perego into the system of Ware for the benefit of avoiding lost clock cycles and improves electronic system efficiency and performance characteristics, even when the commands are transmitted at different times. (Perego, [0199]).
Claim(s) 16 is directed to method steps that implement the system claim 3, and therefore the corresponding mappings are incorporated.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ellis et al.(2005/0081543) where a refresh logic carries out refresh operation on a row within the storage array during time period during which no transactions are carried out by external memory controller(Ellis, 0031).
Response to Arguments
Applicant's arguments filed 4/9/2026 have been fully considered but they are not persuasive.
Regarding the non-statutory double patenting rejection of claims 2-21, the applicant contends that the present claims are substantially distinct from the claims of 1-20 of US Patent No. 10,510,395 which is the parent of the instant application(Remarks, p. 9).
The USPTO disagrees with this characterization. This is a non-statutory double patenting rejection. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s)(MPEP 804(II)(b)).
For the purposes of this discussion, the present application claims will be referred to as “instant” and the parent patent as “parent”.
For example regarding claim(s) 2, 10 and 15 of the instant, the specification of the instant demonstrates that the “progress information” feature exists to enable the same bank-dependent sequence/timing concept already claimed in the parent, making claim 2 an obvious variation of the patented invention. See MPEP 804(II)(B)(1).
The non-statutory double patenting rejection is further clarified in the DP rejection section earlier in this action. Based on the mentioned analysis, the DP rejection is maintained.
Regarding the rejections under 35 USC 112(a), the USPTO drops the prior rejection pertaining to claim(s) 9, 10-14 and 21, and maintains the rejection for 3, 11 and 16. The analysis is shown in the 112(a) rejection section above.
Regarding the rejections under 35 USC 112(b), the USPTO drops the prior rejection pertaining to claim(s) 9, 10-14, 21.
Regarding claims 2, 10 and 15 the applicant contends that the prior art of Ware in view of Remaklus does not teach the following limitation(Remarks, p. 15, 16):
“…wherein the logic is to sequence the issuance of the commands addressed to the second one of the banks, relative to issuance of the commands addressed to the first one of the banks, in a manner dependent on progress information, received from the DRAM device, indicating that the first one of the banks is undergoing a refresh operation…”.
The USPTO disagrees with this point. The claim language is stating that the memory controller is issuing access commands in an order based on information of whether a bank that is to be accessed, is undergoing a refresh operation. Remaklus discloses an entry bank address latch and an exit bank address latch, where either in a self-refresh mode or auto refresh mode, the refresh starts at the entry bank address latch loaded by the memory controller and increments until a pre-determined number of banks have been refreshed, where the exit bank address latch holds the address of the last bank refreshed, being accessible to the memory controller(Remaklus, 0018, 0032). This means that access operations to the banks will be delayed until the bank is refreshed, which means the sequence of access commands can be affected(Remaklus, 0012, 0040). For instance, programming of several banks can be delayed if in a parallel bank retrieval system, one bank is being refreshed, while other banks are being accessed(Remaklus, 0040). The entry bank address latch, counter, and exit bank address latch are the collection of “progress information”, that may be retrieved from the exit bank address latch, that indicate that the DRAM is undergoing a refresh operation. The applicant’s claims do not specify how the progress information can be read by the memory controller relative with the DRAM undergoing the refresh operation. Therefore Remaklus teaches the limitation. The rejection(s) are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/ Primary Examiner, Art Unit 2132
Prosecution Insights