Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 7: 705. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 sets forth “memory cells each selectively coupled to a bitline”. Claim 1 also sets forth “each access sense amplifier selectively coupled to one of the bitlines”, and “each preset circuit selectively coupled to one of the bitlines”. There is insufficient antecedent basis for “the bitlines”. The claim sets forth “memory cells each selectively coupled to a bitline”, indicating that each of the memory cells is selectively coupled to the same bitline. Antecedent basis is only provided for “a bitline”. Therefore, “the bitlines” does not have antecedent basis. Appropriate clarification is required.
Claims 2-8 are rejected as dependent upon claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9, 12-13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR20170088138A (Son, et al., hereinafter Son).
Regarding claim 9, Son teaches a method for accessing and presetting memory cells in a dynamic, random-access memory (DRAM), (Son, FIG. 1-9; [0007]: “9 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure”; [0024]: “As a random access memory, the memory device 100 may include a dynamic random access memory (DRAM) cell.”) the DRAM including rows and column of memory cells and storage (Son, [0030]: “the memory device 100 includes a memory cell array 110, control logic 120, an address register 130, a row decoder 140, a column decoder 160, a read / write circuit 150, An input / output buffer 170, and a data pattern providing unit 180.”) for a preset pattern, (Son, [0043]: “In the embodiments, the data pattern providing unit 180 includes a pattern buffer 181 that stores a plurality of predetermined data patterns,”) the method comprising: receiving a preset command with an address specifying one of the rows of memory cells; (Son, [0076]: “When the pattern write command and the address signal are received from the memory controller 200 in step S120, the memory device 100 may generate the data pattern, that is, a predetermined data pattern in response to the pattern write command (S130).”) reading the preset pattern from the storage responsive to the preset command; (Son, [0076]: “The memory device 100 may select a data pattern corresponding to the pattern write command from the pattern buffer 181 and output it or may expand the selected data pattern to generate a new data pattern.”) and writing the preset pattern to the specified row of memory cells. (Son, [0077]: “The memory device 100 writes the data pattern in a memory area corresponding to the received address signal (S140).”)
Regarding claim 12, Son teaches the method of claim 9, wherein the storage for the preset pattern comprises ones of the memory cells. (Son, [0028]: “The memory device 100 does not receive the data DATA from the memory controller 200 but generates data internally generated based on the pattern write command”; [0086]: “The memory controller 200 may store information on the data pattern or may store the data pattern in the pattern buffer 220 provided therein.”)
Regarding claim 13, Son teaches the method of claim 12, wherein the storage for the preset pattern comprises one of the rows of memory cells. (Son, [0028]: “The memory device 100 does not receive the data DATA from the memory controller 200 but generates data internally generated based on the pattern write command”; [0086]: “The memory controller 200 may store information on the data pattern or may store the data pattern in the pattern buffer 220 provided therein.” The teachings of Son include that the pattern buffer may be implemented by any configuration of the rows of memory cells.)
Regarding claim 15, Son teaches a dynamic, random-access memory (DRAM) device comprising: rows of memory cells; (Son, [0024]: “The memory device 100 can be applied to a random access memory requiring a high processing speed. As a random access memory, the memory device 100 may include a dynamic random access memory (DRAM) cell. The memory device 100 may be a DRAM chip including a DRAM cell.”) and local control circuitry to write a preset pattern to a range of the rows of memory cells responsive to a preset command that specifies at least one of the rows of memory cells. (Son, [0076]: “When the pattern write command and the address signal are received from the memory controller 200 in step S120, the memory device 100 may generate the data pattern, that is, a predetermined data pattern in response to the pattern write command (S130).”; (Son, [0043]: “In the embodiments, the data pattern providing unit 180 includes a pattern buffer 181 that stores a plurality of predetermined data patterns,”; Son, [0077]: “The memory device 100 writes the data pattern in a memory area corresponding to the received address signal (S140).”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR20170088138A (Son, et al., hereinafter Son) in view of US 20110267917 A1 (Manning).
Regarding claim 10, Son teaches the method of claim 9, but does not appear to explicitly teach wherein the preset command specifies a range of the rows of memory cells, the range including the specified one of the rows of memory cells.
Manning cures the deficiencies of Son. Manning teaches wherein the preset command specifies a range of the rows of memory cells, the range including the specified one of the rows of memory cells. (Manning, [0041]: “Memory device 600 may be constructed with memory cells 625-1 . . . 625-M on row 630 effectively partitioned into groups, where each group is coupled to a different one of the access-lines 635-1, 635-2 . . . 635-N assigned to row 630. Each group may have the same number of memory cells of row 630. Alternatively, the number of memory cells of row 630 for each group may vary. The number of memory cells in a group may range from one memory cell of row 630 to all but one memory cell of row 630.”)
Manning teaches a command to specify a range of the rows of memory cells including a specified memory cell. Both Son and Manning are directed to memory devices and one of ordinary skill in the art would find it obvious to combine the method of Son including writing a preset pattern to a memory cell with the memory cell ranges of Manning with the motivation of improving functionality of the memory device.
Regarding claim 11, Son/Manning teaches the method of claim 10, further comprising writing the preset pattern to all the rows of memory cells within the range of the rows of memory cells responsive to the preset command. (Son teaches writing the preset pattern, and Manning teaches configuring any number of rows or group of rows with a command; Manning, [0044]: “Other rows in memory array 620 may be configured in a similar manner as row 630. Memory array 620 may include a plurality of rows 630 . . . 630-R. Similar to row 630, each row has a plurality of access-lines, where each access-line of the respective row is coupled to one or more memory cells on the respective row to operatively access the one or more memory cells without accessing other memory cells on the respective row.”)
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR20170088138A (Son, et al., hereinafter Son) in view of US 20090251982 (Ware).
Regarding claim 14, Son teaches the method of claim 12, but does not appear to explicitly teach further comprising refreshing the one of the rows of memory cells.
Ware cures the deficiencies of Son. Ware teaches further comprising refreshing the one of the rows of memory cells. (Ware, [0049]: “As noted above, the DRAM circuit performs self-refresh row by row. Thus, the bulk of the self-refresh energy is stored in the hundreds or even thousands of bit lines coupled to a row of memory cells being refreshed. Slowly ramping a single word line does not conserve much energy. Therefore, operation 420 may be optional in some embodiments.”)
Son and Ware are both directed to DRAM circuits and more generally memory devices. It would have been obvious to one of ordinary skill in the art to combine the teachings of Son with the self-refresh of Ware in order to improve efficiency of the memory device.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR20170088138A (Son, et al., hereinafter Son) in view of US 20030063516 (Jain).
Regarding claim 16, Son teaches the DRAM device of claim 15, and Son does teach wherein the circuit may include a plurality of sense amplifiers. (Son, [0037]: “The read / write circuit 150 includes a write circuit 151 and a read circuit 152 and is capable of writing data to the memory cell array 110 or reading data from the memory cell array 110. [ For example, the write circuit 151 may include a plurality of write drivers, and the read circuit 152 may include a plurality of sense amplifiers.”). However, Son does not appear to explicitly teach further comprising a first row of sense amplifiers coupled to the rows of memory cells and a second row of sense amplifiers coupled to the rows of memory cells, the second row of sense amplifiers to convey the preset pattern to the rows of memory cells.
Jain cures the deficiencies of Son. Jain (FIG. 1-5; Jain, [0013]: “The memory array comprises a sense amplifier bank 15 having a plurality of sense amplifiers. A sense amplifier corresponds or is coupled to a column of memory cells.”) teaches a first row of sense amplifiers coupled to the rows of memory cells and a second row of sense amplifiers coupled to the rows of memory cells, (Jain, [0013]: “A sense amplifier corresponds or is coupled to a column of memory cells.”) the second row of sense amplifiers to convey the preset pattern to the rows of memory cells. (Jain, [0016]: “The charge stored within the storage nodes of the memory cells of the refreshed words in row m are sensed and amplified by the corresponding sense amplifiers of sense amplifier bank and written back into the memory cells.”)
Jain teaches sensing and amplifying data through the use of sense amplifiers. It would be obvious to one of ordinary skill in the art to combine the teachings of Jain with the DRAM device of Son in order to transmit a pattern to memory cells. One of ordinary skill in the art would have a motivation to modify the teachings of Son to improve efficiency of a DRAM device.
Allowable Subject Matter
Claims 1-8 are rejected as indefinite, and further search and consideration is required upon resolution of indefiniteness issues before any indication of allowable subject matter.
Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 17, the prior art of record does not appear to teach a dynamic, random-access memory (DRAM) device comprising: rows of memory cells; and local control circuitry to write a preset pattern to a range of the rows of memory cells responsive to a preset command that specifies at least one of the rows of memory cells, further comprising a first row of sense amplifiers coupled to the rows of memory cells and a second row of sense amplifiers coupled to the rows of memory cells, the second row of sense amplifiers to convey the preset pattern to the rows of memory cells, wherein each of the sense amplifiers in the first row of sense amplifiers is connected in parallel, between a pair of bitlines, with one of the sense amplifiers in the second row of sense amplifiers.
Regarding claim 18, the prior art of record does not appear to teach a dynamic, random-access memory (DRAM) device comprising: rows of memory cells; and local control circuitry to write a preset pattern to a range of the rows of memory cells responsive to a preset command that specifies at least one of the rows of memory cells, the local control circuitry to interrupt the write of the preset pattern responsive to an access request.
Regarding claim 19, the prior art of record does not appear to teach a dynamic, random-access memory (DRAM) device comprising: rows of memory cells; and local control circuitry to write a preset pattern to a range of the rows of memory cells responsive to a preset command that specifies at least one of the rows of memory cells, the local control circuity to read the preset pattern from one of the rows of memory cells to write the preset pattern to the range of the rows of memory cells.
Regarding claim 20, the prior art of record does not appear to teach a dynamic, random-access memory (DRAM) device comprising: rows of memory cells; and local control circuitry to write a preset pattern to a range of the rows of memory cells responsive to a preset command that specifies at least one of the rows of memory cells, wherein the rows of memory cells are in a first bank of memory cells and the DRAM device further comprises a second bank of memory cells with second rows of memory cells, the local control circuitry to write a second preset pattern to a second range of the rows of memory cells in the second bank of memory cells.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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