DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20, submitted on 1/15/2025, is acknowledged and considered.
Claims 1, 12, and 18 are independent claims. Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/15/2025 was filed after the mailing date of the claims on 1/15/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
4. Claim 11 is objected to because of the following informalities:
Claim 11, recite the acronym “CXL”, but fails to provide what the acronym stands for or if the CXL is a label to that of the claimed controller.
Appropriate correction is required.
Allowable Subject Matter
5. Claims 7, 10, 16-17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1-6, 8-9, 11-15, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyle [US 7242766] in view of Sethumadhavan, et al. [US 9887833].
As per claim 1: Lyle teaches a receiving device comprising:
a cryptographic circuit comprising an Advanced Encryption Standard (AES) engine [Lyle: col 14, line 65-col 15, line 12; the cipher outputs and inputs are connected in different ways in different operational modes. Among the operational modes for the AES algorithm are "Counter" (CTR) and "Output Feedback" (OFB) modes. The CTR mode of AES is well suited for encryption of data transmitted over a DVI or TMDS link (and for decryption of the transmitted data) because it is easily pipelined, and its security characteristics are both good and verifiable] with a fixed epoch size [Lyle: col 16, line 25-31; synchronous operation used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references). The data transmission that includes timing references suggest fixed epoch size] and a fixed latency for integrity and data encryption (IDE) [Lyle: col 36, line 14-20; The pipeline within block cipher is filled before block cipher can assert data useful by XOR unit for encrypting (or decrypting) video data, because it has a fixed latency and must assert useful data to XOR unit by the time that unit receives the first pixel of each quantity (e.g., each line) of video data to be encrypted], wherein the cryptographic circuit to: [Lyle: col 30, line 5-6]
send a delay parameter to a transmitting device, the delay parameter representing a number of clock cycles corresponding to the fixed latency; [Lyle: col 16, line 4-15; In cryptography, encryption and decryption occur at different times, which requires that some kind of synchronization is included in the message transmitted over the link. "Instantaneous" links (or links with known or predictable delays) can be implemented to operate asynchronously. See also col 36, line 45-60]
**pre-determine, using the AES engine, AES data for a first epoch [**rejected under the secondary reference, discussion below] before first input data of the first epoch is received from the transmitting device; [Lyle: Col 26, line 17-25; AES content protection protocol to encrypt data transmitted over paths. The content source sends encrypted, compressed data (e.g., video data) over paths, and router sends the encrypted, compressed data over path to receiver. Thus, AES content or encrypted data suggest the AES data before the input data is received]
receive, after the number of clock cycles, the first input data from the transmitting device; and [Lyle: col 15, line 65-col 16, line 30; the cipher can be run faster (e.g. using a faster clock or more pipelining) or more data can be processed during each interval of time (e.g., the size of each block of pseudo-random values generated during a processing period of N clock cycles can be doubled, to double the throughput of the PRNG function). Or, additional cipher blocks can be added to process more data at the same time. In cryptography, encryption and decryption most often occur at different times (this is known as "asynchronous" operation), which requires that some kind of synchronization is included in the message transmitted over the link]
determine first output data for the first epoch [Lyle: col 5, line 15-25; performs one round of a block cipher per clock cycle to assert a different pair of 28-bit round keys each clock cycle in response to the output of LFSR module, and Round Function B performs one round of a block cipher per clock cycle, to assert a different pair of 28-bit round keys each clock cycle. Col 16, line 25-31; synchronous operation used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references). The data transmission that includes timing references suggest output data of the first epoch] using the AES data and the first input data without storing the AES data in a buffer. [Lyle: col 38, line 27-33; AES-128 CTR encrypted video data are transmitted over a TMDS-like link, and decrypted at the other end of the link, the encryption and decryption need to be synchronous, and to occur simultaneously (so that the encrypted data can be decrypted for display without the need to use buffer memory capable of storing more than a small quantity of the encrypted data)]
Lyle teaches synchronous operation can be used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references) [Lyle: col 16. line 25-31]. The data transmission that includes timing references suggest output AES content protection protocol to encrypt data transmitted over paths. Also, the content source sends encrypted, compressed data (e.g., video data) over paths, and router sends the encrypted, compressed data over path to receiver [Lyle: col 26, line 17-25]. Thus, the encrypted data transmitted is AES data that is before the input data received. However, Lyle does not clearly teach “pre-determine, using the AES engine, AES data for a first epoch”.
Sethumadhavan teaches an invention including identifying a process to obtain timing information of a processor-based device. Further, include returning a timing information value corresponding to a time stamp counter (TSC) value at the end of the period equal to the sum of the remainder of the clock cycles in the current epoch interval and the random-based portion of the clock cycles in the following epoch interval [Sethumadhavan: col 2, line 15-40]. Sethumadhavan obviously suggest “pre-determined, using the AES engine, AES data for a first epoch”, where one would be motivated to identify the process to obtain the timing information and further perform operations that include disabling one or more countermeasures to identify and respond to one or more processes attempting to obtain timing information for the processor-based device. Sethumadhavan also discusses the epochs have non-uniform lengths that are chosen randomly as a value in a range between 2.sup.e−1 clock cycles and 2.sup.e−1 clock cycles, where e is a predetermined value representative of a level of timing information obfuscation. For example, if e is set to a value of 10, a particular epoch may have a randomly chosen length/duration between 2.sup.9 to (2.sup.10−1), i.e., 512 to 1023 clock cycles [Sethumadhavan: col 7, line 28-37].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Sethumadhavan with Lyle to teach “pre-determine, using the AES engine, AES data for a first epoch” for the reason to identify the process to obtain the timing information, in order to perform operations that include disabling one or more countermeasures to identify and respond to one or more processes attempting to obtain timing information for the processor-based device [Sethumadhavan: col 6, line 1-20 and 60-63].
Claim 2: Lyle: col, 16, line 25-31 in view of Sethumadhavan: col 7, line 28-37 [suggesting “the first epoch is pre-determined”, under the same pretext and motivation as in claim 1]; discussing the receiving device of claim 1, wherein the cryptographic circuit is further to pre-determine AES input data for the first epoch before the AES data for the first epoch is pre-determined.
Claim 3: Lyle: col, 16, line 25-31; discussing the receiving device of claim 2, wherein the cryptographic circuit is to pre-determine the AES input data from a counter output.
Claim 4: Lyle: col 17, line 60-67; discussing the e receiving device of claim 1, wherein the first input data is plaintext, and the first output data is ciphertext.
Claim 5: Lyle: col 17, line 60-67; discussing the receiving device of claim 1, wherein the first input data is ciphertext, and the first output data is plaintext.
Claim 6: Lyle: col 35, line 30-47; discussing the receiving device of claim 1, wherein the AES engine comprises a number of levels of a pipeline, wherein the number of levels corresponds to the number of clockcycles.
Claim 7: Objected
Claim 8: Lyle: col 16, line5-32; discussing the receiving device of claim 6, wherein, in response to no data being transferred between the transmitting device and the receiving device, inputs and outputs of the pipeline are stalled at a same time.
Claim 9: Lyle: col 7, line 60-col 8, line 5, col 30, line 23-42; discussing the receiving device of claim 1, wherein the cryptographic circuit is to determine, using the AES engine, an authentication tag associated with the first epoch in parallel with determining the first output data.
Claim 10: Objected
Claim 11: Lyle: col 26, line 15-col 27, line 30, FIG.8; discussing the receiving device of claim 1, further comprising: a CXL controller coupled to one or more hosts and the cryptographic circuit; and a memory controller coupled to a dynamic random access memory (DRAM) device, wherein the cryptographic circuit comprises an in-line memory encryption (IME) block with the AES engine and an error correction code (ECC) block.As per claim 12: Lyle teaches a transmitting device comprising:
a cryptographic circuit comprising an Advanced Encryption Standard (AES) engine [Lyle: col 14, line 65-col 15, line 12; the cipher outputs and inputs are connected in different ways in different operational modes. Among the operational modes for the AES algorithm are "Counter" (CTR) and "Output Feedback" (OFB) modes. The CTR mode of AES is well suited for encryption of data transmitted over a DVI or TMDS link (and for decryption of the transmitted data) because it is easily pipelined, and its security characteristics are both good and verifiable. See also col 30, line 25-45] with a fixed epoch size [Lyle: col 16, line 25-31; synchronous operation used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references). The data transmission that includes timing references suggest fixed epoch size] and a fixed latency for integrity and data encryption (IDE) [Lyle: col 36, line 14-20; The pipeline within block cipher is filled before block cipher can assert data useful by XOR unit for encrypting (or decrypting) video data, because it has a fixed latency and must assert useful data to XOR unit by the time that unit receives the first pixel of each quantity (e.g., each line) of video data to be encrypted], the fixed latency corresponding to a first number of clock cycles, wherein the cryptographic circuit is to: [Lyle: col 4, line 43-45]
**pre-determine, using the AES engine, AES data for a first epoch [**rejected under the secondary reference, discussion below] before first input data of the first epoch is input into the AES engine; [Lyle: Col 26, line 17-25; AES content protection protocol to encrypt data transmitted over paths. The content source sends encrypted, compressed data (e.g., video data) over paths, and router sends the encrypted, compressed data over path to receiver. Thus, AES content or encrypted data suggest the AES data before the input data input or stored]
determine, after the first number of clock cycles [Lyle: col 15, line 65-col 16, line 30; the cipher can be run faster (e.g. using a faster clock or more pipelining) or more data can be processed during each interval of time (e.g., the size of each block of pseudo-random values generated during a processing period of N clock cycles can be doubled, to double the throughput of the PRNG function). Or, additional cipher blocks can be added to process more data at the same time. In cryptography, encryption and decryption most often occur at different times (this is known as "asynchronous" operation), which requires that some kind of synchronization is included in the message transmitted over the link], first output data for the first epoch using the AES data and the first input data without storing the AES data in a buffer; and [Lyle: col 38, line 27-33; AES-128 CTR encrypted video data are transmitted over a TMDS-like link, and decrypted at the other end of the link, the encryption and decryption need to be synchronous, and to occur simultaneously (so that the encrypted data can be decrypted for display without the need to use buffer memory capable of storing more than a small quantity of the encrypted data)]
send the first output data to a receiving device. [Lyle: col 5, line 32-35, col 29, line 10-25]
Lyle teaches synchronous operation can be used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references) [Lyle: col 16. line 25-31]. The data transmission that includes timing references suggest output AES content protection protocol to encrypt data transmitted over paths. Also, the content source sends encrypted, compressed data (e.g., video data) over paths, and router sends the encrypted, compressed data over path to receiver [Lyle: col 26, line 17-25]. Thus, the encrypted data transmitted is AES data that is before the input data received. However, Lyle does not clearly teach “pre-determine, using the AES engine, AES data for a first epoch”.
Sethumadhavan teaches an invention including identifying a process to obtain timing information of a processor-based device. Further, include returning a timing information value corresponding to a time stamp counter (TSC) value at the end of the period equal to the sum of the remainder of the clock cycles in the current epoch interval and the random-based portion of the clock cycles in the following epoch interval [Sethumadhavan: col 2, line 15-40]. Sethumadhavan obviously suggest “pre-determined, using the AES engine, AES data for a first epoch”, where one would be motivated to identify the process to obtain the timing information and further perform operations that include disabling one or more countermeasures to identify and respond to one or more processes attempting to obtain timing information for the processor-based device. Sethumadhavan also discusses the epochs have non-uniform lengths that are chosen randomly as a value in a range between 2.sup.e−1 clock cycles and 2.sup.e−1 clock cycles, where e is a predetermined value representative of a level of timing information obfuscation. For example, if e is set to a value of 10, a particular epoch may have a randomly chosen length/duration between 2.sup.9 to (2.sup.10−1), i.e., 512 to 1023 clock cycles [Sethumadhavan: col 7, line 28-37].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Sethumadhavan with Lyle to teach “pre-determine, using the AES engine, AES data for a first epoch” for the reason to identify the process to obtain the timing information, in order to perform operations that include disabling one or more countermeasures to identify and respond to one or more processes attempting to obtain timing information for the processor-based device [Sethumadhavan: col 6, line 1-20 and 60-63].
Claim 13: Lyle: col 17, line 60-67; discussing the transmitting device of claim l 2, wherein the first input data is plaintext, and the first output data is ciphertext.
Claim 14: Lyle: col 35, line 30-47; discussing the transmitting device of claim 12, wherein the AES engine comprises a number of levels of a pipeline, wherein the number of levels corresponds to the first number of clock cycles.
Claim 15: Lyle: col 7, line 60-col 8, line 5, col 30, line 23-42; discussing the receiving device of claim 1, wherein the cryptographic circuit is to determine, using the AES engine, an authentication tag associated with the first epoch in parallel with determining the first output data.
Claim 16: Objected
Claim 17: Objected
As per claim 18: Lyle teaches a method of operating a receiving device, the method comprising:
sending a delay parameter to a transmitting device, the delay parameter representing a number of clock cycles [Lyle: col 16, line 4-15; In cryptography, encryption and decryption occur at different times, which requires that some kind of synchronization is included in the message transmitted over the link. "Instantaneous" links (or links with known or predictable delays) can be implemented to operate asynchronously. See also col 36, line 45-60] corresponding to a fixed latency of an Advanced Encryption Standard (AES) engine [Lyle: col 14, line 65-col 15, line 12; the cipher outputs and inputs are connected in different ways in different operational modes. Among the operational modes for the AES algorithm are "Counter" (CTR) and "Output Feedback" (OFB) modes. The CTR mode of AES is well suited for encryption of data transmitted over a DVI or TMDS link (and for decryption of the transmitted data) because it is easily pipelined, and its security characteristics are both good and verifiable] with a fixed epoch size [Lyle: col 16, line 25-31; synchronous operation used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references). The data transmission that includes timing references suggest fixed epoch size] for integrity and data encryption (IDE); [Lyle: col 36, line 14-20; The pipeline within block cipher is filled before block cipher can assert data useful by XOR unit for encrypting (or decrypting) video data, because it has a fixed latency and must assert useful data to XOR unit by the time that unit receives the first pixel of each quantity (e.g., each line) of video data to be encrypted]
**pre-determining, using the AES engine, AES data for a first epoch [**rejected under the secondary reference, discussion below] before first input data of the first epoch is received from the transmitting device; [Lyle: Col 26, line 17-25; AES content protection protocol to encrypt data transmitted over paths. The content source sends encrypted, compressed data (e.g., video data) over paths, and router sends the encrypted, compressed data over path to receiver. Thus, AES content or encrypted data suggest the AES data before the input data of the first epoch is received]
receiving, after the number of clock cycles, the first input data from the transmitting device; and [Lyle: col 15, line 65-col 16, line 30; the cipher can be run faster (e.g. using a faster clock or more pipelining) or more data can be processed during each interval of time (e.g., the size of each block of pseudo-random values generated during a processing period of N clock cycles can be doubled, to double the throughput of the PRNG function). Or, additional cipher blocks can be added to process more data at the same time. In cryptography, encryption and decryption most often occur at different times (this is known as "asynchronous" operation), which requires that some kind of synchronization is included in the message transmitted over the link]
determining first output data for the first epoch using the AES data and the first input data without storing the AES data in a buffer. [Lyle: col 38, line 27-33; AES-128 CTR encrypted video data are transmitted over a TMDS-like link, and decrypted at the other end of the link, the encryption and decryption need to be synchronous, and to occur simultaneously (so that the encrypted data can be decrypted for display without the need to use buffer memory capable of storing more than a small quantity of the encrypted data)]
Lyle teaches synchronous operation can be used for encrypting and decrypting video data transmitted over the link (since video data transmission includes transmission of handy timing references) [Lyle: col 16. line 25-31]. The data transmission that includes timing references suggest output AES content protection protocol to encrypt data transmitted over paths. Also, the content source sends encrypted, compressed data (e.g., video data) over paths, and router sends the encrypted, compressed data over path to receiver [Lyle: col 26, line 17-25]. Thus, the encrypted data transmitted is AES data that is before the input data received. However, Lyle does not clearly teach “pre-determine, using the AES engine, AES data for a first epoch”.
Sethumadhavan teaches an invention including identifying a process to obtain timing information of a processor-based device. Further, include returning a timing information value corresponding to a time stamp counter (TSC) value at the end of the period equal to the sum of the remainder of the clock cycles in the current epoch interval and the random-based portion of the clock cycles in the following epoch interval [Sethumadhavan: col 2, line 15-40]. Sethumadhavan obviously suggest “pre-determined, using the AES engine, AES data for a first epoch”, where one would be motivated to identify the process to obtain the timing information and further perform operations that include disabling one or more countermeasures to identify and respond to one or more processes attempting to obtain timing information for the processor-based device. Sethumadhavan also discusses the epochs have non-uniform lengths that are chosen randomly as a value in a range between 2.sup.e−1 clock cycles and 2.sup.e−1 clock cycles, where e is a predetermined value representative of a level of timing information obfuscation. For example, if e is set to a value of 10, a particular epoch may have a randomly chosen length/duration between 2.sup.9 to (2.sup.10−1), i.e., 512 to 1023 clock cycles [Sethumadhavan: col 7, line 28-37].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Sethumadhavan with Lyle to teach “pre-determine, using the AES engine, AES data for a first epoch” for the reason to identify the process to obtain the timing information, in order to perform operations that include disabling one or more countermeasures to identify and respond to one or more processes attempting to obtain timing information for the processor-based device [Sethumadhavan: col 6, line 1-20 and 60-63].
Claim 19: Lyle: col 7, line 60-col 8, line 5; discussing the method of claim 18, further comprising determining, using the AES engine, an authentication tag associated with the first epoch in parallel with determining the first output data.
Claim 20: Objected
Conclusion
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Leynna Truvan
Examiner
Art Unit 2435
/L.TT/Examiner, Art Unit 2435
/EDWARD ZEE/Primary Examiner, Art Unit 2435
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