DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/08/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 11-16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US. Pub. No. 2021/0366389, hereinafter “Liu”) in view of Lee et al. (US. Pub. No. 2014/0146030, hereinafter “Lee”).
As to claim 1, (Original) Liu discloses a data providing circuit [figure 3, data providing circuit 10A], comprising a multiplexing circuit [figure 2, multiplexing circuit 21] and a reset circuit [figure 2, reset circuit 22], wherein N is an integer greater than 1 [figures 2 and 3, N is an integer greater than 1];
wherein the multiplexing circuit is electrically connected to a data voltage providing
terminal, N multiplexing control terminals, and N data lines [figure 3, 21 is electrically connected to a data voltage DATA, N multiplexing control terminals MUX_N and N data lines], and is configured to write a data voltage provided by the data voltage providing terminal into an n-th data line under control of an n-th multiplexing control signal provided by an n-th multiplexing control terminal; n is a positive integer less than or equal to N [figure 3, write DATA into an n-th data line under the control of MUX_N];
wherein the reset circuit is electrically connected to a first multiplexing control terminal,
and data lines other than a first data line in the N data lines, and is configured to control a voltage provided by the voltage line to be written into the data lines other than the first data line in the N data lines under control of a first multiplexing control signal provided by the first multiplexing control terminal [figure 3, reset circuit 22 is electrically connected to a first multiplexing control terminal MUX_1 and data lines other than a first data line in the N data lines, to control a voltage ELVDD provided by the voltage line to be written into the data lines other than the first data line in the N data liens under control of MUX_1 provided by the first multiplexing control terminal].
Liu doesn’t expressly disclose wherein the reset circuit is electrically connected to an initial voltage line, and is configured to control an initial voltage provided by the initial voltage line to be written into the data lines.
Lee teaches a reset circuit is electrically connected to an initial voltage line, and is configured to control an initial voltage provided by the initial voltage line to be written into data lines [figure 2, a reset circuit SW2 is electrically connected to an initial voltage line Vint1 to control an initial voltage Vint1 provided by the initial voltage line to be written into data lines D2, D3].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the data providing circuit of Liu to have the reset circuit electrically connected to an initial voltage line and configured to control an initial voltage provided by the initial voltage line to be written into data lines, as taught by Lee, in order to supply an initialization power source to other data lines except the specific data line (Lee, paragraph 22).
As to claim 2, (Original) Liu, as modified by Lee, discloses the data providing circuit according to claim 1, wherein the reset circuit comprises M reset sub-circuits; M is equal to N-1; m is a positive integer less than or equal to M [Liu, figure 3, the reset circuit comprises 2 reset sub-circuits, M is 2 equal to 3-1, Lee, figure 2, the reset circuit comprises 2 reset sub-circuits, M is 2 equal to 3-1];
wherein a control terminal of an m-th reset sub-circuit is electrically connected to the first
multiplexing control terminal, a first terminal of the m-th reset sub-circuit is electrically connected to the initial voltage line, and a second terminal of the m-th reset sub-circuit is electrically connected to an (m+1)-th data line [Liu as modified by Lee, figure 3, the gate of M2 is connected to MUX_1, first terminal of the first reset sub-circuit is connected to Vint1, second terminal of the first reset sub-circuit is connected to the second data line];
wherein the m-th reset sub-circuit is configured to write the initial voltage provided by the initial voltage line into the (m+1)-th data line under control of the first multiplexing control signal provided by the first multiplexing control terminal [Liu as modified by Lee, figure 3, the first reset sub-circuit is to write Vint1 into the second data line under control of MUX_1]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 3, (Original) Liu, as modified by Lee, discloses the data providing circuit according to claim 1, wherein the multiplexing circuit comprises N multiplexing sub-circuits [Liu, figure 3, the multiplexing circuit comprises 3 multiplexing sub-circuits];
wherein a control terminal of an n-th multiplexing sub-circuit is electrically connected to the n-th multiplexing control terminal, a first terminal of the n-th multiplexing sub-circuit is electrically connected to the data voltage providing terminal, and a second terminal of the n-th multiplexing sub-circuit is electrically connected to the n-th data line [Liu, figure 3, the gate of M1 is connected to multiplexing control terminal, first terminal of M1 is connected to DATA, second terminal of M1 is connected to n-th data line];
wherein the n-th multiplexing sub-circuit is configured to write the data voltage provided by the data voltage providing terminal into the n-th data line under control of the n-th multiplexing control signal provided by the n-th multiplexing control terminal [Liu, figure 3, M1 is to write DATA into the n-th data line under control of MUX_N].
As to claim 4, (Currently Amended) Liu, as modified by Lee, discloses a display substrate, comprising a base and the data providing circuit according to claim 1
As to claim 11, (Currently Amended) Liu, as modified by Lee, discloses a display panel [Liu, figure 7, display panel PA], comprising the display substrate according to claim 4
As to claim 12, (Currently Amended) Liu, as modified by Lee, discloses a display panel [Liu, figure 7, display panel PA comprising data providing circuit 76], comprising the data providing circuit according to claim 1
As to claim 13, (Original) Liu, as modified by Lee, discloses the display panel according to claim 12, further comprising pixel circuits arranged in a plurality of rows and columns in a display region [Liu, figure 7, pixel circuits P arranged in a plurality of rows and columns in a display region];
wherein the pixel circuit comprises a light-emitting element, a drive circuit, and a writing control circuit [Liu, figure 5, a light-emitting element 35, a drive circuit 32, a writing control circuit 31];
wherein the drive circuit is configured to generate a drive current for driving the light- emitting element under control of a potential of a control terminal of the drive circuit [Liu, paragraph 50, The driving sub-circuit 32 is configured to generate the driving current during the light emission phase. The driving current has a magnitude related to the data voltage. Specifically, in this example, the driving sub-circuit 32 includes a driving transistor DTFT including a control electrode, a first electrode, and a second electrode];
wherein the writing control circuit is electrically connected to a scanning line, the data line, and a first terminal of the drive circuit, and is configured to write a data voltage provided by the data line into the first terminal of the drive circuit under control of a scanning signal provided by the scanning line [Liu, figure 5, 31 is connected to scanning line G, data line, and a first terminal of 32, paragraph 51, The compensation sub-circuit 31 is configured to transfer the data voltage (transferred by the multiplexing control circuit 21 of the multiplexing circuit 20B from the data line DATA to the first node N1) to the driving sub-circuit 32 in response to a second scan signal G(n) being active in a compensation phase].
As to claim 14, (Currently Amended) see the above discussion of claim 1.
As to claim 15, (Original) see the above discussion of claim 13.
As to claim 16, (Original) Liu, as modified by Lee, discloses the driving method according to claim 15, wherein a start of the data writing stage coincides with a start of the first writing time period [Liu, figure 6, start of data writing state of DATA coincides with start of first writing time period of MUX_1].
As to claim 19, (Currently Amended) Liu, as modified by Lee, discloses a display device [Liu, figure 7, a display device 70 comprising display panel PA], comprising the display panel according to claim 11-
As to claim 20, (New) see the above discussion of claim 1.
Claim(s) 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee, further in view of Kimura et al. (US. Patent No. 9,990,881, hereinafter “Kimura”).
As to claim 5, (Currently Amended) Liu, as modified by Lee, discloses the display substrate according to claim 4, wherein the reset circuit in the data providing circuit comprises M reset sub-circuits; M is equal to N-1; m is a positive integer less than or equal to M [Liu, figure 3, the reset circuit comprises 2 reset sub-circuits, M is 2 equal to 3-1, Lee, figure 2, the reset circuit comprises 2 reset sub-circuits, M is 2 equal to 3-1];
wherein a control terminal of an m-th reset sub-circuit is electrically connected to the first multiplexing control terminal, a first terminal of the m-th reset sub-circuit is electrically connected to the initial voltage line, and a second terminal of the m-th reset sub-circuit is electrically connected to an (m+1)-th data line [Liu as modified by Lee, figure 3, the gate of M2 is connected to MUX_1, first terminal of the first reset sub-circuit is connected to Vint1, second terminal of the first reset sub-circuit is connected to the second data line]; wherein the m-th reset sub-circuit is configured to write the initial voltage provided by the initial voltage line into the (m+1)-th data line under control of the first multiplexing control signal provided by the first multiplexing control terminal [Liu as modified by Lee, figure 3, the first reset sub-circuit is to write Vint1 into the second data line under control of MUX_1].
Liu as modified by Lee doesn’t expressly disclose wherein a first terminal of a reset sub-circuit in the M reset sub-circuits is further used as a first terminal of another reset sub-circuit in the M reset
Kimura teaches a first terminal of a reset sub-circuit in reset sub-circuits is further used as a first terminal of another reset sub-circuit in the reset sub-circuits [figure 2, a first terminal of RST1 is used as a first terminal of RST2 in the reset sub-circuits].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the data providing circuit of Liu to have a first terminal of a reset sub-circuit in the M reset sub-circuits is further used as a first terminal of another reset sub-circuit in the M reset sub-circuits, as taught by Kimura, since it is a use of known technique to improve similar devices in the same way.
As to claim 6, (Original) Liu, as modified by Lee and Kimura, discloses the display substrate according to claim 5, wherein the multiplexing circuit in the data providing circuit comprises N multiplexing sub-circuits [Liu, figure 3, the multiplexing circuit comprises 3 multiplexing sub-circuits];
wherein a control terminal of an n-th multiplexing sub-circuit is electrically connected to the n-th multiplexing control terminal, a first terminal of the n-th multiplexing sub-circuit is electrically connected to the data voltage providing terminal, and a second terminal of the n-th multiplexing sub-circuit is electrically connected to the n-th data line [Liu, figure 3, the gate of M1 is connected to multiplexing control terminal, first terminal of M1 is connected to DATA, second terminal of M1 is connected to n-th data line]; wherein the n-th multiplexing sub-circuit is configured to write the data voltage provided by the data voltage providing terminal into the n-th data line under control of the n-th multiplexing control signal provided by the n-th multiplexing control terminal [Liu, figure 3, M1 is to write DATA into the n-th data line under control of MUX_N];
wherein the second terminal of the n-th multiplexing sub-circuit is further used as a second terminal of an (n-1)-th reset sub-circuit [Liu, figure 3, the second terminal of the 2nd M1 is further used as a second terminal of a first M2].
As to claim 7, (Currently Amended) Liu, as modified by Lee and Kimura, discloses the display substrate according to claim 6, wherein the m-th reset sub-circuit comprises an m-th reset transistor [Liu, figure 3, the m-th reset sub-circuit M2 comprises an m-th reset transistor M2];
wherein a gate electrode of the m-th reset transistor is electrically connected to the first multiplexing control terminal, a first electrode of the m-th reset transistor is electrically connected to the initial voltage line, and a second electrode of the m-th reset transistor is electrically connected to the (m+1)-th data line [Liu modified by Lee, figure 3, gate of M2 is connected to MUX_1, first electrode of M2 is connected to Vint1 and second electrode of M2 is connected to (m+1)-th data line];
wherein a first electrode of a reset transistor in M reset transistors is further used as a first electrode of another reset transistor in the M reset
As to claim 8, (Original) Liu, as modified by Lee and Kimura, discloses the display substrate according to claim 7, wherein the n-th multiplexing sub-circuit comprises an n-th multiplexing transistor [Liu, figure 3, the n-th multiplexing sub-circuit comprises an n-th multiplexing transistor M1];
wherein a gate electrode of the n-th multiplexing transistor is electrically connected to the n-th multiplexing control terminal, a first electrode of the n-th multiplexing transistor is electrically connected to the data voltage providing terminal, and a second electrode of the n-th multiplexing transistor is electrically connected to the n-th data line [Liu, figure 3, gate of M1 is connected to n-th multiplexing control terminal MUX_n, first electrode of M1 is connected to DATA and second electrode of M1 is connected to n-th data line];
wherein the second electrode of the n-th multiplexing transistor is further used as a second electrode of an (n-1)-th reset transistor [Liu, figure 3, second electrode of M1 is further used as a second electrode of (n-1)-th reset transistor M2].
As to claim 9, (Original) Liu, as modified by Lee and Kimura, discloses the display substrate according to claim 8, wherein N is equal to 3, and M is equal to 2 [Liu, figure 3, N is equal to 3 and M is equal to 2];
wherein a first electrode of a first reset transistor is further used as a first electrode of a second reset transistor [Kimura, figure 2, first electrode of RST1 is further used as first electrode of RST2];
wherein the first electrode of the first reset transistor is further used as a second electrode of a second multiplexing transistor, and a second electrode of the second reset transistor is further used as a second electrode of a third multiplexing transistor [Liu, figure 3, first electrode of M2 (second row) is further used as a second electrode of M1, second electrode of M2 (third row) is further used as second electrode of third multiplexing transistor M1].
Allowable Subject Matter
Claims 10 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combination limitations of dependent claims 10 and 17-18, such as “wherein N is equal to 5, and M is equal to 4; wherein a first electrode of a first reset transistor is further used as a first electrode of a second reset transistor, and a first electrode of a third reset transistor is further used as a first electrode of a fourth reset transistor; wherein the first electrode of the first reset transistor is further used as a second electrode of a second multiplexing transistor, and a second electrode of the second reset transistor is further used as a second electrode of a third multiplexing transistor; the first electrode of the third reset transistor is further used as a second electrode of a fourth multiplexing transistor, and a second electrode of the fourth reset transistor is further used as a second electrode of a fifth multiplexing transistor”, recited by claim 10; “wherein the display cycle further comprises a pre-writing stage; the pre-writing stage is before the data writing stage, and the pre-writing stage is immediately adjacent to the data writing stage; the driving method comprises: in the pre-writing stage, controlling, by the reset circuit, the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line in the N data lines under control of the first multiplexing control signal, and writing, by the multiplexing circuit, the data voltage provided by the data voltage providing terminal into the first data line under control of the first multiplexing control signal”, recited by claim 17; and “controlling the data voltage provided by the data voltage providing terminal to be Va+Va during an n-th writing time period, where a is an integer less than or equal to N and greater than 1; wherein Va is equal to (Va-Vth-V0) X (e-(t1-t⁰a)/RC) -e-(t1/RC)), wherein Vth is a threshold voltage of a drive transistor comprised in the drive circuit, and Va is a data voltage required to be written into an a-th data line during the a-th writing time period; wherein tl is a duration of the data writing stage, and t0a is equal to (a-1) X (t2+t3), wherein t2 is a duration of each writing time period, t3 is an interval time between two adjacent writing time periods, R is a resistance value of a resistor on the data line, C is a capacitance value of a coupling capacitor on the data line, and V0 is a voltage on the data lines after the reset circuit controls the initial voltage provided by the initial voltage line to be written into the data lines other than the first data line in the N data lines under control of the first multiplexing control signal”, recited by claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US. Patent No. 12,148,390) is considered as pertinent art to claim 1 regarding the reset circuit as seen in figure 4A
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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/NAN-YING YANG/ Primary Examiner, Art Unit 2629
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