Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4 September 2026 has been entered.
Specification
The disclosure is objected to because of the following informalities:
The amendment filed 10 June 2026 replaced paragraph [0017] in its entirety, and the replacement paragraph ends with the sentence [e.g., Instant Specification Paragraph 17: In another related embodiment, the programming signals sets can be on either side for each section.], omitting the eight sentences that follow it in paragraph [0017] as filed —
[e.g., Instant Specification Paragraph 17: The data come to update the display also include the section that will be updated.] [e.g., Instant Specification Paragraph 17: The data are directed to sections intended for update and the signals for that sections are activated.] [e.g., Instant Specification Paragraph 17: The data signals may include biasing conditions, data inputs and frame rate.] [e.g., Instant Specification Paragraph 17: Programming signals include the select signals that activate the pixel for accepting programing data, emission signals that control the emission time and frame rate of the pixel.] [e.g., Instant Specification Paragraph 17: Also, each section can have a different emission duty cycle optimized for the brightness, power or colour of that section.] [e.g., Instant Specification Paragraph 17: The pixel may have compensation techniques that can be controlled in section or individually.] [e.g., Instant Specification Paragraph 17: The compensation technique is used to improve the pixel performance such as uniformity, reliability under prolonged use or different environmental conditions.] [e.g., Instant Specification Paragraph 17: The environmental conditions can be temperature, ambient light and so on.].
Under 37 CFR 1.121(b)(1) a replacement paragraph replaces the entire paragraph, so those sentences are no longer part of the specification of record, although they are the descriptive counterparts of the select and emission signals of claim 1, the data signals of claim 6 and the emission duty cycle of claim 8, and although Applicant’s remarks of 10 June 2026 and 4 September 2026 cite paragraph [0017] for language found only in the omitted sentences.
The omitted sentences are present in the application as filed, so their restoration introduces no new matter; written-description support is assessed against the application as filed and is unaffected.
The description of record must nonetheless describe the claimed subject matter and give the claim terms clear support (37 CFR 1.71(a); MPEP § 608.01(o)); restoring the omitted sentences would do so.
Appropriate correction is required.
Claim Interpretation
The following readings are applied under the broadest reasonable interpretation consistent with the specification.
(a) Section: a portion of the pixel array treated as a programming unit; the specification places no minimum size on a section [e.g., Instant Specification Paragraph 18: sections as small as one pixel]. In the grounds below the claimed section is one cluster of Cok, and it is that same cluster in every limitation.
(b) More than one row of sections and more than one column of sections is given effect as written: the sections occupy more than one section row and more than one section column in the same arrangement.
(c) Emission signals that control an emission time and a frame rate of the pixel: the emission time is the duration for which the pixel is driven to emit within a driving operation, and the frame rate is the cadence at which the pixel’s frame-driving operation repeats, including the case in which a pixel holds its previously driven state through intervening intervals; the rate at which update data arrives from a host and the repetition frequency of a pulse-width-modulation carrier are not the frame rate of the pixel. The specification recites both functions of the emission signals together [e.g., Instant Specification Paragraph 17, as filed: emission signals that control the emission time and frame rate of the pixel] without defining frame rate or requiring the emission signals to act alone.
(d) The data for updating the display including a beginning and an end of the section: the update data must bound the same section that the set of programming signals selects; the specification states that the segment information may be [e.g., Instant Specification Paragraph 23: the beginning and end of a sub-array] or, in the alternative, [e.g., Instant Specification Paragraph 23: the start point and the number of rows and columns], and the remarks filed 4 September 2026 invoke the same pair of alternatives, so information conveying a beginning together with a sufficient extent satisfies the limitation, while a bare identifier naming a section, a purely temporal end-of-transmission marker, or bounds computed entirely within the display from transmitted information that locates nothing would not.
(e) An orientation of the respective set of programming signals for each section is different (claim 4): orientation is read in its ordinary sense of the relative position or direction in which the set of programming signals is arranged with respect to the array. The specification uses the term for the arrangement of the programming signals relative to the array [e.g., Instant Specification Paragraph 17, as filed: However, it can be noted that the orientation can be different.] and illustrates sets of programming signals that differ by the side of the section from which they are arranged [e.g., Instant Specification Paragraph 17, as filed: In another related embodiment, the programming signals sets can be on either side for each section.; Fig. 1: 110 and 114 (left), 112 and 116 (right)]; the claim recites that the orientation differs from section to section — that it is not the same for every section — and not that any set runs in a particular direction or that every section’s orientation is distinct from every other’s.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1–4, 6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation “the section of the sub-array sections to be updated” (in the clause beginning “the data for updating the display including a beginning and an end of”).
There is insufficient antecedent basis for this limitation in the claim:
claim 1 earlier recites “at least a section of the sub-array sections to be updated” and later recites “the at least a section”.
The claim is amenable to two or more plausible constructions.
Under one, only one section is to be updated (the limitation “the section of the sub-array sections to be updated”), and the recited beginning and end are those of that section;
under another, two or more sections may be updated (the limitation “at least a section of the sub-array sections to be updated”), and
it would then be unclear to one having ordinary skill in the art whether the recited beginning and end are those of each such section, of one of them, or of the group of them taken together.
Where a claim is amenable to two or more plausible constructions, the applicant is required to more precisely define the metes and bounds of the claimed invention, and the claim is rejected as indefinite.
Ex parte Miyazaki, 89 USPQ2d 1207 (Bd. Pat. App. & Inter. 2008) (precedential); MPEP §§ 2173.02 and 2173.05(b).
Claim 6 recites the limitation “data signals” (line 1).
The claim is amenable to two or more plausible constructions: it would be unclear to one having ordinary skill in the art whether the “data signals” are intended to refer to the earlier recited “data for updating a display” (claim 1), to the earlier recited “programming data” (claim 1), or to a further class of signals not otherwise recited, and the scope of claim 6 differs under each reading.
Where a claim is amenable to two or more plausible constructions, the applicant is required to more precisely define the metes and bounds of the claimed invention, and the claim is rejected as indefinite.
Ex parte Miyazaki, 89 USPQ2d 1207 (Bd. Pat. App. & Inter. 2008) (precedential); MPEP §§ 2173.02 and 2173.05(b).
For the purpose of applying the prior art below, the term is read in the sense the specification gives it — the data signals delivered to the display for updating it, whatever interface carries them [e.g., Instant Specification Paragraph 17, as filed: The data signals may include biasing conditions, data inputs and frame rate.] — which is the broadest of the three readings.
Claims 2-4, 6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being dependent upon rejected base claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Cok et al (US 2023/0196979 A1) in view of Cho et al (US 2022/0020327 A1) and Yadav et al (US 2019/0089927 A1).
Regarding claim 1, Cok discloses a method to update a section of pixel arrays, the method comprising:
having a pixel array divided into sub-array sections [e.g., Paragraph 110: each cluster 70 includes a contiguous two-dimensional sub-array of pixels 20 that includes fewer than all of pixels 20] including
more than one row of sections and more than one column of sections, [e.g., Paragraph 35: transmit cluster packets to ones of the clusters comprising at least some different rows at the same time; Fig. 25: clusters 70] [e.g., Paragraph 35: transmit cluster packets to ones of the clusters comprising at least some different columns at a same time]
wherein each section of the sub-array sections is connected to a respective set of programming signals, [e.g., Paragraph 108: a cluster row controller 24A and a cluster column controller 24B] [e.g., Paragraph 107: unique wire or unique combination of wires] and
wherein the respective set of programming signals corresponding to a section is activated to select that section for programming; [e.g., Paragraph 79: When a pixel 20 is selected by row-select line 42] [e.g., Paragraph 115: Cluster controller 24 receives the cluster packet and reads the packet address. If the packet address matches the cluster address, the packet data in the cluster packet is stored in cluster memory 26] [e.g., Paragraph 109: cluster controller 24 can provide active-matrix control to pixels 20 in cluster 70] and
updating a programming data for each section independently, [e.g., Paragraph 112: display controller 72 is operable to selectively update display 99 with a number of cluster packets that is fewer than the number of clusters 70] [e.g., Paragraph 111: to some but not all of clusters 70 in any order]
wherein data for updating a display is indicative of at least a section of the sub-array sections to be updated with respective programming data, [e.g., Paragraph 70: image data (e.g., pixel data) is transmitted to only some and not all of the pixels in a display in a single refresh cycle] [e.g., Paragraph 115: Cluster controller 24 receives the cluster packet and reads the packet address. If the packet address matches the cluster address, the packet data in the cluster packet is stored in cluster memory 26]
the data for updating the display including a beginning [e.g., Paragraph 41: a start address, a count, and a number of pixel values corresponding to the count; Fig. 22C: Offset, Count] [e.g., Paragraph 125: a start address, a count and a number of pixel values corresponding to the count, for example specifying a two-dimensional subset of pixels 20 in a cluster 70]
wherein the respective set of programming signals corresponding to the at least a section includes select signals that activate a pixel for accepting the respective programming data, [e.g., Paragraph 79: data received from column-data line 32 is stored in pixel memory 26]
emission signals that control an emission time [e.g., Paragraph 87: the length of time an LED 50 emits light]
Cok does not expressly disclose
(i) that the emission signals control a frame rate of the pixel, as that term is read in paragraph 4(c) above: Cok’s timing signals are directed to emission duration [e.g., Paragraph 87: The timing signals (e.g., PWM signals) can be used to control the length of time an LED 50 emits light], and
Cok’s separate teaching of refreshing on demand [e.g., Paragraph 111: display 99 can be a refresh-on-demand display 99 and, further, can refresh only changing portions on demand in display 99] concerns the cadence at which packets are transmitted to a cluster, which is the arrival rate of update data rather than the pixel’s frame-driving cadence; and
(ii) that the data for updating the display include an end of the section to be updated.
As to (ii), the packet address of Cok’s cluster packet identifies the cluster to be updated [e.g., Paragraph 115: Cluster controller 24 receives the cluster packet and reads the packet address. If the packet address matches the cluster address, the packet data in the cluster packet is stored in cluster memory 26],
the start address the packet carries is a value relative to the pixels of that cluster, a zero offset referring to the cluster’s first pixel [e.g., Paragraph 125: The start address can be a value relative to the pixels 20 in cluster 70 (e.g., a zero offset or address value can refer to the first pixel 20)], and
a packet that updates the whole cluster carries the pixel values for all of its pixels [e.g., Paragraph 112: a single communication (e.g., comprising a single packet cluster) contains all of the pixel values necessary to update all of pixels 20 in each cluster 70];
the start address and the count [e.g., Paragraph 41: a start address, a count, and a number of pixel values corresponding to the count; Fig. 22C: Offset, Count] [e.g., Paragraph 125: a start address, a count and a number of pixel values corresponding to the count, for example specifying a two-dimensional subset of pixels 20 in a cluster 70] therefore convey, under the reading in paragraph 4(d) above, the beginning of the section together with its extent.
To the extent the claim is read to require that the end of the section be conveyed as such, Cok does not expressly disclose it, and Yadav is relied on for it.
Cho is of record and was applied in the final action mailed 7 July 2026 for the data for updating a display; it is applied here for a different teaching, and the earlier application is not carried forward into this rejection.
Cho teaches emission driving signals whose own frequency differs between regions of the display, and that a region driven at the lower frequency holds the state established by the preceding driving operation.
Cho discloses driving the emission lines of a first display region and of a second display region at different driving frequencies [e.g., Paragraph 69: may drive light emission lines corresponding to the first display region DA1 among the light emission lines EML1 to EMLn at a first driving frequency, and may drive light emission lines corresponding to the second display region DA2 at a second driving frequency different from the first driving frequency in response to the light emission control signal ECS],
gives the frequencies expressly [e.g., Paragraph 104: during the low power mode, the frequency of the light emission driving signals EM1 to EM1920 is 120 Hz, and the frequency of the light emission driving signals EM1921 to EM3840 is 1 Hz],
ties them to the content of each region [e.g., Paragraph 105: The first display region DA1 in which a moving image is displayed is driven by the light emission driving signals EM1 to EM1920 of a normal frequency (e.g., 120 Hz) and the second display region DA2 in which a still image is displayed is driven by the light emission driving signals EM1921 to EM3840 of a low frequency (e.g., 1 Hz).], and
discloses that the pixel retains its driven state while the emission driving signal of the low-frequency region is masked [e.g., Paragraph 101: while a light emission driving signal EM1921 is maintained to be at a low level in the fourth frame F4, the fifth transistor T5 (see FIG. 3) and the sixth transistor T6 (see FIG. 3) may be maintained to be turned on].
Cok and Cho are analogous art: both are directed to driving arrays of light-emitting display pixels and to reducing the power consumed in refreshing content that is not changing.
Cok identifies the problem in those terms [e.g., Cok, Paragraph 70: This display refresh consumes energy, reduces lifetime, and wastes resources] and
already distinguishes clusters whose content has changed from those whose content has not [e.g., Cok, Paragraph 111: Portions of display 99 can be refreshed or updated when corresponding portions of an image displayed on display 99 change but not all of pixels 20 in display 99 are updated or refreshed];
Cho addresses the same problem one step further along, reducing not the transfer of data to a region but the frequency at which that region’s pixels are driven to emit, expressly for still-image content and expressly to reduce power [e.g., Cho, Paragraph 102: This driving scheme allows for embodiments to reduce power consumption without deterioration in display quality of the display device DD].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the emission timing circuitry of Cok’s clusters at region-dependent frequencies as Cho teaches, so that the frame-driving operation of a cluster whose content is not changing recurs at a lower cadence, that cluster holding the emission state set by its preceding driving operation as Cho’s low-frequency region does [e.g., Cho, Paragraph 101: the light emitting diode ED (see FIG. 3) may be maintained in a light emission state of a previous frame], while a cluster whose content is changing is driven at the normal cadence.
What is taken from Cho is the per-region cadence at which the driving operation recurs — Cho drives each region as a whole at its own frequency [e.g., Cho, Paragraph 177: during a low power mode, the first display region DA1 illustrated in FIG. 1 may be driven at a normal frequency (e.g., 120 Hz) and the second display region DA2 illustrated in FIG. 1 may be driven at a low frequency (e.g., 1 Hz)];
the emission time within each driving operation continues to be set by Cok’s own timing signals [e.g., Cok, Paragraph 87: The timing signals (e.g., PWM signals) can be used to control the length of time an LED 50 emits light],
which each pixel’s timing circuit generates internally and independently from the value the pixel stores [e.g., Cok, Paragraph 88: each pixel 20 can comprise a pixel timing circuit 28 that internally and independently generates a timing signal controlling the brightness of pixel 20], and the stored value is unchanged between operations.
This is the combination of prior-art elements according to known methods to yield predictable results, and the use of a known technique to improve a similar device in the same way.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
A reasonable expectation of success is supplied by Cok itself, which stores a value in each pixel [e.g., Cok, Paragraph 79: data received from column-data line 32 is stored in pixel memory 26] and provides local per-cluster timing circuitry [e.g., Cok, Paragraph 124: cluster timing circuits 28], so that the state a cluster holds between driving operations is already maintained in Cok’s own architecture; the combination operates Cok’s per-cluster timing circuitry at region-dependent cadences and does not place Cho’s full-width emission lines across Cok’s clusters.
Yadav teaches that, for a partial refresh in which some blocks of a display receive new content while other blocks are refreshed from panel memory, the host identifies each block to the panel by transmitting the block’s beginning and its end.
Yadav discloses that the host determines which blocks are refreshed with new content and which are refreshed from memory [e.g., Paragraph 53: host processor 16 determines blocks which shall be refreshed on-the-fly (from e.g., host processor 16) and which blocks shall be refreshed offline] [e.g., Paragraph 53: a block is said to be refreshed offline if display panel 18 refreshes the block from panel memory 40 without receiving updated display content of the block from host processor 16],
that the host identifies a block by transmitting its starting and ending lines [e.g., Paragraph 53: host processor 16 may identify the block to display panel 18 by signaling a line range (e.g., starting and ending rows or starting and ending columns)],
that a rectangular block may instead be identified by the coordinates of its corners [e.g., Paragraph 54: blocks are region based (e.g., based on rectangular, circular, or amorphous regions and may be signaled based on pixel coordinates of corners, pixel coordinates of a central point in a circular region and a pixel radius, or pixel outlines, respectively)], and
that the regions so identified are refreshed at different rates [e.g., Paragraph 49: a block-based timing engine may determine that blocks (e.g., regions) of a display frame are high-refresh-rate regions] [e.g., Paragraph 50: display controller 46 refreshes display screen 36 by multiplexing content data for high-refresh-rate regions with content data for low-refresh-rate regions].
Yadav is analogous art to Cok and Cho: it is directed to refreshing only the changing portion of a display in order to save power [e.g., Yadav, Paragraph 21: Not resending the unchanged portions of the display content may reduce the amount of electrical energy consumed by the computing device], which is the field of endeavor of both and the problem each addresses.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to convey, in Cok’s cluster packet, the beginning and the end of the cluster to be updated, as Yadav teaches signaling the starting and ending rows or columns, or the corner coordinates, of the block to be refreshed, because Yadav states the purpose of doing so — the panel thereby knows which block the transmitted content belongs to and which blocks are to be refreshed from memory — and because Cok’s addressed packet must likewise determine the position and extent of the pixels it writes [e.g., Cok, Paragraph 125: a start address, a count and a number of pixel values corresponding to the count, for example specifying a two-dimensional subset of pixels 20 in a cluster 70].
In the combination the block of Yadav is the cluster of Cok itself, a rectangular region whose location and pixels are fixed by design [e.g., Cok, Paragraph 122: Since clusters 70 can be disposed in fixed locations on substrate 10, their locations and pixels 20 can likewise be fixed as a matter of display 99 design], so that the beginning and the end conveyed are those of the section selected by that cluster’s own set of programming signals, not of a subset of pixels within it.
The modification substitutes one known convention for expressing the limits of a region for another, and would have yielded no more than the predictable result of identifying the same region by its two limits rather than by one limit and a length.
KSR, 550 U.S. 398.
Regarding claim 2, Cok discloses the respective set of programming signals for each section are arranged in rows [e.g., Paragraph 108: a cluster row controller 24A and a cluster column controller 24B] [e.g., Paragraph 75: provides control signals (e.g., row-select signals) and/or timing signals (e.g., clocks or timing signals such as pulse-width modulation (PWM) signals) through row-select lines 42 to rows 14 of pixels 20] [e.g., Paragraph 114: The same transmission and connection designs can be applied to cluster 70 as are described above with respect to pixels 20 and each cluster controller 24 can provide active- or passive-matrix control to pixels 20 in cluster 70] and
data lines are arranged in columns. [e.g., Paragraph 79: data received from column-data line 32 is stored in pixel memory 26]
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cok in view of Cho and Yadav as applied to claim 1 above, and further in view of Yamashita et al (US 2018/0075808 A1).
Regarding claim 3, Cok discloses sub-array sections on a right side [e.g., Paragraph 110: Clusters 70 can be disposed in an array having rows 14 of clusters 70 and columns 16 of clusters 70; Fig. 25: clusters 70]
Cok, Cho and Yadav do not expressly disclose that the sections on a right side are connected to right programming signals and the sections on a left side are connected to left programming signals;
Cok’s clusters are arranged in rows and columns of clusters, each cluster served by its own row and column controllers [e.g., Cok, Paragraph 108: a cluster row controller 24A and a cluster column controller 24B], without stating on which side of the array the signals of a given cluster are placed.
Yamashita teaches that allocation for both signal types: the gate driver to the left of the active area addresses the pixels on the left half and the gate driver to the right addresses the pixels on the right half [e.g., Yamashita, Paragraph 57: the gate driver 52 to the left of the active area may be used to address pixels on the left half of the display, and the gate driver 52 to the right of the active area may be used to address pixels on the right half of the display], and
likewise the emission driver on each side addresses the pixels on its half [e.g., Yamashita, Paragraph 57: Similarly, the emission driver 54 to the left of the active area may be used to address pixels on the left half of the display].
Yamashita is analogous art, being directed to driving a divided display array with per-section scan and emission drivers to reduce power, and it treats the placement of that driver circuitry as a matter of design [e.g., Yamashita, Paragraph 58: gate driver circuitry 20B may be formed on only one side of the active area, on three or more sides of the area, or in any other desired location within the electronic device].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place the sets of programming signals of Cok’s clusters on the side of the array each cluster occupies, as Yamashita allocates the drivers on each side to the pixels on that half, in order to shorten the lines over which each cluster’s programming signals propagate — the consideration Cok itself applies to the lines that serve its clusters [e.g., Cok, Paragraph 119: to reduce the length of column-data lines 32 over which signals propagate] — the predictable result of an arrangement Yamashita expressly adopts.
KSR, 550 U.S. 398.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cok in view of Cho and Yadav as applied to claim 1 above;
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Cok in view of Cho and Yadav as applied to claim 1 above, and further in view of Lee et al (US 2021/0090503 A1).
Regarding claim 4, Cok discloses an orientation of the respective set of programming signals for each section is different. [e.g., Paragraph 117: clusters 70 (comprising pixels 20 that are either active-matrix or passive-matrix controlled by cluster controller 24, e.g., with cluster row and column controllers 24A, 24B) are connected in parallel with a single column-data line 32; Fig. 25: clusters 70, 32] [e.g., Paragraph 117: Clusters 70 can be connected in columns 16 with each column 16 of clusters 70 connected to display controller 72, as shown in FIG. 25] [e.g., Paragraph 115: uniquely connect and uniquely communicate with each cluster 70]
Under the reading set out in paragraph 4(e) above, the set of programming signals of each of Cok’s clusters — its own cluster row controller and cluster column controller and the wires that uniquely connect it — is arranged at, and enters from, the position of that cluster in the array, so that the orientation of a section’s set relative to the array is not the same for every section — the claim reciting that the orientation is different for the sections, not a pairwise-distinct orientation for each of them.
Should it be shown that Cok discloses an orientation of the respective set of programming signals for each section being different with insufficient specificity:
Lee discloses sets of programming signals whose orientation differs from section to section — in the second and third areas of its display the gate lines through which the scan signals SCAN(N−1) and SCAN(N) and the signal EM are applied —
Lee’s EM being the signal that controls the emission time of the emitting device [e.g., Lee, Paragraph 61: A fifth transistor T5 may be controlled by the scan signal EM and electrically connect the second node N2 of the driving transistor DRT and the emitting device ED. The fifth transistor T5 may control emission times of the emitting device ED] —
extend in a horizontal direction [e.g., Lee, Paragraph 131: in the second area A2 and the third area A3 among the upper areas of the active area A/A, the second gate lines GL2, through which the scan signals SCAN(N−1), SCAN(N), and EM and the like are applied, may extend in a horizontal direction; Fig. 8: A2, A3],
while in the first area the gate lines through which the same signals are applied extend in a vertical direction intersecting them [e.g., Lee, Paragraph 132: In the first area A1, the first gate lines GL1, through which the scan signals SCAN(N−1), SCAN(N), and EM and the like are applied, may extend in a vertical direction intersecting the second gate lines GL2; Fig. 8: A1],
the first area driven through its own gate lines by a first gate driver above the active area and the other areas through the second gate lines by a second gate driver to its left, so that the two sets also enter the array from different sides [e.g., Lee, Paragraph 113: The first gate driver 121 driving the subpixels SP of the first area A1 may be disposed on a first side of (e.g. above) the active area A/A. In addition, the second gate driver 122 driving the second area A2, the third area A3, and the fourth area A4 may be disposed on a second side (e.g. to the left) of the active area A/A].
Lee is analogous art, being directed to driving the areas of a display array through separate gate lines [e.g., Lee, Paragraph 86: the area having the first resolution and the area having the second resolution in the active area A/A may be driven through different gate lines GL].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to run the set of programming signals of one of Cok’s clusters in a direction different from that of another, as Lee teaches for its areas —
the two directions being interchangeable in Cok’s own array [e.g., Cok, Paragraph 72: Horizontal and vertical are arbitrary orthogonal directions] —
in order to facilitate the placement of the driver and the lines that serve that section [e.g., Lee, Paragraph 134: since the first gate lines GL1 for driving the first area A1 extend in a direction intersecting the second gate lines GL2, the placement of the first gate driver 121 and the first gate lines GL1 for driving the first area A1 may be facilitated] and
to confine those lines to the section they serve [e.g., Lee, Paragraph 117: the first gate lines GL1 separately disposed for the driving of the first area A1 may only be disposed in the first area A1] — the predictable result of an arrangement Lee expressly adopts.
KSR, 550 U.S. 398.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cok in view of Cho and Yadav as applied to claim 1 above, and further in view of Yoon et al (US 2023/0260449 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Cok in view of Cho and Yadav as applied to claim 1 above, and further in view of ILI Technology Corp., ILI9341 Data Sheet V1.02 (6 December 2010) (“ILI9341”).
Regarding claim 6, Cok discloses data signals include a start address, a count, and a number of pixel values corresponding to the count]
Cok does not expressly disclose that the data signals include biasing conditions or frame rates: Cok’s cluster packet carries a packet address, an offset, a count and pixel values [e.g., Cok, Paragraph 41: a start address, a count, and a number of pixel values corresponding to the count], and Cok does not state that the packet, or any other data signal, includes a biasing condition or a frame rate.
Yadav, already in the combination, teaches that the instructions the host sends to the panel with the identification of the blocks to be refreshed carry the refresh timing of those blocks — the host sends instructions designating which blocks are refreshed with new content and which from panel memory [e.g., Yadav, Paragraph 50: host timing engine 30 may send instructions to panel timing engine 38 to bypass panel memory 40 and to send data directly to display screen 36 for specific high-refresh blocks and/or to refresh display screen 36 with pixel data stored in panel memory 40 for other low-refresh blocks] [e.g., Yadav, Paragraph 50: Instructions may also include refresh/timing information.] — so that the data for updating the display include the frame rates at which the identified blocks are refreshed.
In the combination the cluster packet that identifies the cluster to be updated carries that refresh timing with it, as Yadav’s instructions carry the refresh/timing information with the block identification, so that the cadence at which each cluster is driven – the region-dependent cadence taken from Cho – is set by the data delivered to that cluster; the reason is Yadav’s own, that the panel refreshes the identified blocks at the rates the host delegates.
Neither Cok, Cho nor Yadav expressly discloses that the data signals include a biasing condition; Cho’s only biasing is the forward biasing of a transistor inside the pixel circuit, a circuit condition rather than content of the data signals.
Yoon teaches it.
Yoon drives a first display area at a normal or higher frequency and a second display area at a lower frequency to reduce power [e.g., Yoon, Paragraph 60: The display device DD may reduce power consumption by lowering a driving frequency of the second display area DA2.],
with the frequencies of the two areas set by mode information received from outside [e.g., Yoon, Paragraph 145: the operating mode determiner 110 may determine the operating mode based on mode information included in the control signal CTRL provided from the outside (e.g., a main processor or a graphics processor)] [e.g., Yoon, Paragraph 145: The mode signal MD may include information about the first driving frequency of the first display area DA1 and the second driving frequency of the second display area DA2].
Yoon’s driving controller outputs the image data and the control signals from that mode information [e.g., Yoon, Paragraph 146: The signal generator 120 outputs the output image signal DATA, the data control signal DCS, the emission control signal ECS, and the scan control signal SCS in response to the input image signal RGB, the control signal CTRL, and the mode signal MD.], and,
in the multi-frequency mode, outputs bias signals in the same data stream as the image data [e.g., Yoon, Paragraph 149: While the mode signal MD indicates the multi-frequency mode, the signal generator 120 may sequentially output the output image signal DATA, a first bias signal B1AS1, and a second bias signal BIAS2.] [e.g., Yoon, Paragraph 133: the driving controller 100 provides the data driving circuit 200 with the output image signal DATA corresponding to a bias signal],
so that the data signal applied to the pixels of the low-frequency area during its non-driving period is a bias voltage [e.g., Yoon, Paragraph 157: a data signal of a first voltage level Vbias1 (shown in FIG. 10) corresponding to the first bias signal BIAS1 may be provided to pixels of the boundary area BR belonging to the second display area DA2],
applied to the first electrode of the driving transistor to initialize its gate-source voltage without rewriting the stored image data [e.g., Yoon, Paragraph 169: The gate-source voltage of the first transistor T1 (refer to FIG. 5) may be initialized by providing the second voltage level Vbias2 corresponding to the second bias signal BIAS2 to the first electrode of the first transistor T1 during the non-driving period NDRP].
Yoon gives the purpose: decreasing the luminance difference due to an afterimage at the boundary between the two areas [e.g., Yoon, Paragraph 151: a driving method for decreasing a luminance difference due to an afterimage at a boundary between the first and second display areas DA1 and DA2].
Yoon is analogous art, being directed to driving the areas of a display at different frequencies to reduce power, the field of endeavor of Cok, Cho and Yadav and the problem each addresses.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include, in the data signals delivered to the clusters of Cok as modified by Cho and Yadav, bias signals for the clusters held at the lower cadence, as Yoon teaches outputting bias signals with the image data for the area driven at the lower frequency, in order to keep the driving transistors of the held clusters biased and thereby to reduce the luminance difference between clusters driven at different cadences — the reason Yoon states.
The cluster controller of Cok, which has its own control logic [e.g., Cok, Paragraph 108: cluster controller 24 can comprise a cluster row controller 24A and a cluster column controller 24B (and, optionally, additional control logic)], would apply the bias signal it receives to the driving transistors of its pixels in the intervals between driving operations, as Yoon applies it in the non-driving period, leaving the stored pixel values untouched, with the predictable result of data signals that include biasing conditions, data inputs and frame rates.
KSR, 550 U.S. 398.
In the alternative, should it be found that the combination with Yoon does not teach that the data signals include biasing conditions and frame rates:
ILI9341, the data sheet of a display driver, teaches it.
ILI9341 discloses a serial interface between a host and the display driver over which the host reads and writes command, parameter or display data [e.g., ILI9341, page 33, § 7.1.8: Read/Write command, parameter or display data.],
the host writing commands or data to the driver [e.g., ILI9341, page 33, § 7.1.9: The write mode of the interface means that host writes commands or data to ILI9341.]
with each transmission byte stored either as display data or as a command parameter [e.g., ILI9341, page 33, § 7.1.9: If the D/CX bit is “high”, the transmission byte is stored as the display data RAM (Memory write command), or command register as parameter.].
Over that one interface the host transfers the pixel data to the driver’s frame memory [e.g., ILI9341, page 114, § 8.2.22: This command is used to transfer data from MCU to frame memory.] — the data inputs —
sets the reference level for the VCOM level and the grayscale voltage level [e.g., ILI9341, page 178, § 8.3.16: Set the GVDD level, which is a reference level for the VCOM level and the grayscale voltage level.] and the VCOMH voltage [e.g., ILI9341, page 180, § 8.3.18: Set the VCOMH voltage.] — biasing conditions —
and sets the frame rate by the Frame Rate Control command [e.g., ILI9341, page 155, § 8.3.2: Frame Rate Control (In Normal Mode/Full Colors) (B1h)] [e.g., ILI9341, page 155, § 8.3.2: Formula to calculate frame frequency] — the frame rates.
ILI9341 is analogous art, being directed to the data interface by which a host delivers display data and the driving settings for that data to a display, which is the interface Cok’s cluster packets serve [e.g., Cok, Paragraph 125: a wide variety of data representation, compression, and storage methods can be used to efficiently transfer cluster packets and packet data].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include, in the data signals delivered to the clusters of Cok as modified by Cho and Yadav, the bias-voltage and frame-rate settings for each cluster together with its pixel data, as ILI9341 carries the VCOM, power and frame-rate settings over the same data interface as the display data, so that the one interface a cluster already has conveys every setting it needs to display its content at its cadence — the use of a known technique to improve a similar device in the same way — with the predictable result of data signals that include biasing conditions, data inputs and frame rates.
KSR, 550 U.S. 398.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cok in view of Cho and Yadav as applied to claim 1 above, and further in view of Long et al (US 2021/0407424 A1).
Regarding claim 8, Cok discloses each section of the sub-array sections has The timing signals (e.g., PWM signals) can be used to control the length of time an LED 50 emits light] [e.g., Paragraph 124: cluster timing circuits 28]
Cok does not expressly disclose that each section has a different emission duty cycle, or that the duty cycle is set for modifying the brightness, power or colour of a respective section:
Cok’s pulse-width timing sets the emission time of each pixel to the brightness it stores [e.g., Cok, Paragraph 87: The timing signals (e.g., PWM signals) can be used to control the length of time an LED 50 emits light] [e.g., Cok, Paragraph 88: each pixel 20 can comprise a pixel timing circuit 28 that internally and independently generates a timing signal controlling the brightness of pixel 20], without stating that different clusters are given different duty cycles for the brightness, power or colour of a cluster.
Cho drives its two regions with emission driving signals of different frequency [e.g., Cho, Paragraph 104: during the low power mode, the frequency of the light emission driving signals EM1 to EM1920 is 120 Hz, and the frequency of the light emission driving signals EM1921 to EM3840 is 1 Hz] and
holds one region’s emission state while the other is pulsed [e.g., Cho, Paragraph 101: light emission driving signals EM1921 to EM3840 are masked at a low level] [e.g., Cho, Paragraph 100: the light emission driving stages EST0 to ESTn sequentially output the light emission driving signals EM1 to EMn in each of frames F1, F2, and F3],
which differentiates the regions’ emission cadence rather than expressly stating a different duty cycle set for a region’s brightness, power or colour;
Yadav does not address emission timing.
Long teaches it.
Long discloses that the brightness of a pixel unit is adjusted by controlling the pulse width of the light-emission control pulse signal [e.g., Long, Paragraph 84: the light-emission brightness of the pixel unit PU that adopts the pixel circuit 100 may be adjusted by controlling the pulse width of the light-emission control pulse signal],
that this pulse width follows the pulse width of the start signal supplied to the region’s light-emission control scan driving circuit [e.g., Long, Paragraph 95: the pulse width of the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA may be adjusted by adjusting the pulse width of the start signal ESTV, so that the light-emission time of the corresponding pixel unit PU may be adjusted],
that each of two display regions has its own light-emission control scan driving circuit triggered by its own start signal [e.g., Long, Paragraph 177: the first light-emission control scan driving circuit EMDC1 is triggered by the first start signal ESTV1 to sequentially output the first light-emission control pulse signals EM1] [e.g., Long, Paragraph 178: the second light-emission control scan driving circuit EMDC2 is triggered by the second start signal ESTV2 to sequentially output the second light-emission control pulse signals EM2],
that the pulse widths of the two start signals may be different [e.g., Long, Paragraph 180: the pulse width of the first pulse signal (the first start signal ESTV1 in FIG. 17) and the pulse width of the second pulse signal (the second start signal ESTV2 in FIG. 17) may also be different; Fig. 17: ESTV1, ESTV2], and
that the difference is set to adjust the brightness of one region relative to the other [e.g., Long, Paragraph 181: in order to improve the overall brightness uniformity of the primary screen and the secondary screen, the brightness of the primary screen needs to be increased or the brightness of the secondary screen needs to be reduced] [e.g., Long, Paragraph 181: by causing the pulse width of the second start signal ESTV2 to be larger than the pulse width of the first start signal ESTV1, the brightness of the primary screen may be made closer to the brightness of the secondary screen].
Long is analogous art, being directed to driving a display region by region with a separate light-emission control scan driving circuit for each region, to reduce power and to manage the brightness of each region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to give the emission signals of each of Cok’s clusters its own pulse width, as Long gives the emission control pulse signals of each of its regions its own width through a separately applied start signal, so that the width of one section differs from that of another as its brightness requires — the purpose Long states — with the predictable result of a different emission duty cycle for each section.
The term each … different is read consistently with the specification, which describes a duty cycle set section by section [e.g., Instant Specification Paragraph 17, as filed: each section can have a different emission duty cycle optimized for the brightness, power or colour of that section]; within the period of a section’s driving operation a different width of the emission-control pulse is a different fraction of that period for which the section’s pixels emit, that is, a different emission duty cycle, the width being set relative to that section’s own period as Long sets its two start-signal widths within one frame [e.g., Long, Paragraph 180: the pulse width of the first pulse signal (the first start signal ESTV1 in FIG. 17) and the pulse width of the second pulse signal (the second start signal ESTV2 in FIG. 17) may also be different; Fig. 17: ESTV1, ESTV2].
KSR, 550 U.S. 398.
Response to Arguments
Applicant’s arguments with respect to claims 1–4, 6 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Cho is applied above only for its teaching of emission driving signals whose frequency differs between regions of the display, which Applicant’s remarks of 4 September 2026 do not address; the data for updating a display, the beginning and the end of the section to be updated, and the independent updating of the sections, which the remarks do address, are met above by Cok and Yadav, not by Cho.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Jin et al (KR 10-2021-0144400 A) relates to a gate driving circuit that selects a start line and an end line of each region of a display and drives the regions at different frame frequencies.
Wacyk et al (US 2018/0075811 A1) relates to a display whose row and column scanners are configured by software command with the start and stop positions of the rows and columns of the region to be written during a frame.
Kim et al (US 2015/0054800 A1) relates to a partial display area whose start row and end row are set to a register of the display controller.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
26 September 2026
