Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/07/2026 and 01/17/2025 was considered by the examiner.
Claim Objections
Claims 10, 13 and 14 are objected to because of the following informalities:
With regard to claim 10, the claim is objected to because the presently amended text repeats 'at least a part of a subsurface damaged layer is removed' on both sides of 'and/or.' The repetition is redundant and appears inconsistent with the alternative structure of original claims 10, 13 and 14.
Applicant is required to delete the redundant language or identify the intended second alternative. No rejection under 35 U.S.C. 112(b) is made because the literal scope remains reasonably ascertainable.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4 and 6 - 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (WO 2021/025085 A1) in view of Horiai et al. (JP 2021-088469 A), and further in view of Geng et al. (Journal of Semiconductors 43(10), 102801).
With regard to claim 1, Kaneko teaches 'removing at least a part of a subsurface damaged layer present in a semiconductor substrate' (the claimed subsurface damaged layer corresponding to machining-induced strain layer 101 beneath the surface of SiC raw substrate 10). The layer includes scratches 1011, latent scratches 1012, and strain 1013 introduced by slicing, grinding, and polishing, and Kaneko thermally removes the layer from the SiC substrate, Kaneko [0038]-[0039], [0190], [0195], [0198], [0201]-[0202], (Figures 8 & 17, see elements 10, 101, 1011, 1012 & 1013).
Kaneko also teaches 'removing at least a part of macro-step bunching present in the semiconductor substrate' by heat-treatment/etching that decomposes existing macro-step bunching on the SiC surface, Kaneko [0017], [0019], [0050]-[0051], [0213]-[0215], (Figures 18 & 19).
Kaneko, however, does not expressly teach 'a photoluminescence measurement step of acquiring distribution information of crystal defects of the semiconductor substrate by photoluminescence measurement.'
Horiai teaches the missing photoluminescence-measurement limitation by irradiating a SiC wafer with excitation light, photographing the in-plane PL-intensity distribution as a two-dimensional image, and identifying the distribution of threading edge dislocations 21, threading screw dislocations 22, and basal-plane dislocations 23 from image contrast, Horiai [0002], [0013], [0026], (Figures 5 & 6, see elements 21, 22 & 23). The claim does not require Horiai's preferred spectral ratio or a particular detection wavelength.
Geng teaches the claimed suppression purpose/effect by establishing that machining-induced subsurface damage in 4H-SiC is a spatially localized PL-black feature under UV illumination; Geng's DIC and UV-PL images show the same subsurface-damage site, Geng p. 1, Abstract, (Figure 1(d)). This evidence supplies the terminology and causal bridge between a nonuniform machining-damage layer and a nonuniform component of the PL background; it is not used as an inherent finding.
In view of the utility of nondestructively acquiring the spatial distribution of crystal defects while reducing PL contrast attributable to machining-induced subsurface damage, it would have been obvious to a person of ordinary skill in the art before the effective filing date to apply Horiai's two-dimensional PL inspection to Kaneko's post-removal SiC substrate and to do so for the PL-quality reason evidenced by Geng. Kaneko supplies the known surface-conditioning operation, Horiai supplies the known nondestructive defect-distribution measurement, and Geng supplies the known relationship between SiC subsurface damage and spatial PL contrast, thereby predictably obtaining a defect-distribution image in which at least the SSD-originating component of background variation is reduced.
With regard to claim 4, for the limitations inherited from claim 1, refer to the rejection of claim 1 above. Kaneko further teaches that the subsurface damaged layer is removed by thermal etching: heat-treatment step S1 etches SiC raw substrate 10 using a temperature gradient and removes strain layer 101, Kaneko [0013]-[0016], [0050], [0201]-[0202], (Figure 17).
With regard to claim 6, Kaneko further teaches that the required macro-step bunching removal is performed by thermal etching during heat-treatment step S1, Kaneko [0017], [0019], [0050]-[0051], [0213]-[0215], (Figures 18 & 19).
With regard to claim 7, Kaneko further teaches heating the SiC substrate under a SiC-Si equilibrium vapor-pressure environment in which formation of macro-step bunching is decomposed and suppressed, Kaneko [0017], [0019]-[0020], [0251], [0254], (Figure 22).
With regard to claim 8, Kaneko further teaches that the macro-step bunching removal step forms regularly arranged surface steps having a height of approximately 1.0 nm, the full-unit-cell height of 4H-SiC and therefore 'one unit cell or less,' Kaneko [0041], [0213]-[0215], [0246], [0254], (Figures 18, 19 & 22).
With regard to claim 9, for the limitations inherited from claim 1, refer to the rejection of claim 1 above. Kaneko's semiconductor substrate is silicon carbide, i.e., a compound semiconductor substrate, Kaneko [0011], [0035].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (WO 2021/025085 A1) in view of Horiai et al. (JP 2021-088469 A) and Geng et al. (Journal of Semiconductors 43(10), 102801), as applied to claim 1 above, and further in view of Kerr et al. (US 2008/0261401 A1).
With regard to claim 5, for the limitations inherited from claim 1, refer to the rejection of claim 1 above. Kaneko teaches thermal removal of machining-induced strain layer 101 but does not expressly teach the added alternative of 'removing at least a part of the subsurface damaged layer by wet etching and/or chemical mechanical polishing.'
Kerr teaches the missing chemical-mechanical-polishing limitation by polishing SiC with an oxidizing solution and colloidal abrasive to remove residual subsurface damage and obtain a surface without the subsurface scratch network, Kerr [0007]-[0012], [0017]-[0018], [0022]-[0023], (Figure 1).
In view of the utility of removing processing-induced SiC damage using established polishing chemistry and equipment, it would have been obvious to a person of ordinary skill in the art before the effective filing date to use Kerr's chemical-mechanical polishing as a known alternative or adjunct to Kaneko's thermal strain-layer removal before performing Horiai's PL inspection, thereby predictably providing a SiC substrate from which at least part of the subsurface damaged layer has been removed by CMP and on which crystal-defect distribution information can be acquired.
Claims 10, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (WO 2021/025085 A1) in view of Horiai et al. (JP 2021-088469 A).
With regard to claim 10, Kaneko teaches a SiC semiconductor substrate from which at least part of a subsurface damaged layer has been removed. Specifically, machining forms subsurface strain layer 101 containing scratches 1011, latent scratches 1012, and strain 1013, and Kaneko thermally removes that layer, Kaneko [0038]-[0039], [0190], [0195], [0198], [0201]-[0202], (Figures 8 & 17, see elements 10, 101, 1011, 1012 & 1013).
Kaneko, however, does not expressly teach 'performing photoluminescence measurement on' the post-removal semiconductor substrate.
Horiai teaches performing photoluminescence measurement on a SiC semiconductor wafer to acquire its two-dimensional in-plane dislocation distribution, including threading edge dislocations 21, threading screw dislocations 22, and basal-plane dislocations 23, Horiai [0002], [0013], [0026], (Figures 5 & 6, see elements 21, 22 & 23).
In view of the utility of nondestructively confirming the spatial crystal-defect condition of a processed SiC substrate before device fabrication, it would have been obvious to a person of ordinary skill in the art before the effective filing date to apply Horiai's PL measurement to Kaneko's post-removal SiC substrate, thereby predictably acquiring two-dimensional crystal-defect distribution information from a substrate having at least part of its machining-induced subsurface damaged layer removed.
With regard to claim 13, the limitations inherited from claim 10, please refer to the rejection of claim 10 above. In the same treated-surface embodiment, Kaneko teaches a post-treatment SiC substrate having no macro-step bunching and regularly arranged 1.0-nm full-unit-cell steps, Kaneko [0213]-[0215], (Figures 18 & 19).
Kaneko further states that the treatment which decomposes the macro-step bunching can also remove the strain layer [0215], thereby linking the one-unit-cell surface to the damaged-layer-removal substrate required by claim 10; Kaneko [0246], [0254], (Figure 22).
With regard to claim 14, for the limitations inherited from claim 10, please refer to the rejection of claim 10 above. Kaneko and Horiai each use a SiC substrate, which is a compound semiconductor substrate, Kaneko [0011], [0035]; Horiai [0002], [0013].
Conclusion
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/DJURA MALEVIC/Examiner, Art Unit 2884
/UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884
