DETAILED ACTION
This Non-final action is responsive to the following communications: application filed on 01/21/2025.
Claims 1-20 are pending. Claim 1 is independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103 and once a reference teaching product appearing to be substantially identical is made the basis of a rejection, and the examiner presents evidence or reasoning tending to show inherency, the burden of proof shifts to the applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
3. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 01/21/2025. This IDS has been considered.
Specification Objections
5. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7a. Claim 1 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, for In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure.
For claim 1, omitted elements and omitted essential structural cooperative relationships of elements (in association with underlined limitations) are as follows:
Claim 1 describe “storage device” without the description of “memory cell”, array (related to storage device) and “memory cell” structure incorporating volatile component, non-volatile component, and switches. See Fig. 1-28 where cell level structure and functions are described. Claim 1 is devoid of this. Overall arrangement of the apparatus (See Fig. 29-Fiug. 30) and function is unclear and vague without the description of cell structure and array layout. Such description is critical and essential because:
1) Throughout spec NV SRAM device is described as inventive concept and functional features of such is being claimed. See e.g., claim 3 where “cell voltage” is being used to describe device operation.
2) Cell structure with volatile and non-volatile components allows write and restore operations.
3) All functions and biasing of the device are performed at transistor level and unit VCMA component level: see e.g., dependent claims describe such. Thus, the presence of the memory cell, it’s structure and boundary is critical. The storage device is not functional with these components at cell level.
7b. All dependent claims inclusive of claims 1-20 are rejected under this category.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gupta et al . (US 2021/0158859 A1).
Regarding independent claim 1, Gupta teaches a storage device (Fig. 7: 10 “NV-SRAM Device”. See e.g., para [0058]) comprising:
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a volatile storage unit (Fig. 7: 11 “SRAM bit-cell”. See para [0057]-para [0058]) that complementarily holds data (See e.g., in context of para [0012], para [0015]: data is written “writing” from SRAM bit-cell to NV bit-cell and “restored” from NV bit-cell to SRAM bit-cell. Data transfer between SRAM bit-cell and NV bit-cell is utilized according to operational requirements); and
a voltage-controlled magneto-resistive effect element (Fig. 7: 14 “NV bit-cell” with VCMA element. See para [0059]) that holds the data complementarily held in the volatile storage unit (See e.g., in context of para [0012], para [0015]: data is written “writing” from SRAM bit-cell to NV bit-cell and “restored” from NV bit-cell to SRAM bit-cell. Data transfer between NV bit-cell and SRAM bit-cell is utilized according to operational requirements).
Regarding claim 18, Gupta teaches the storage device according to claim 1, wherein the volatile storage unit is a latch circuit (Fig. 7 and para [0044]: sram cross coupled inverter in sram cell is a latch).
Regarding claim 20, Gupta teaches the storage device according to claim 1, wherein the volatile storage unit is a static random access memory (SRAM) (Fig. 7 and para [0044]: SRAM).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claims 2-6, and 8-9 is/are rejected under 35 U.S.C. 103 as being obvious over Gupta et al . (US 2021/0158859 A1), in view of HSU (US 2019/0244666 A1).
Regarding claim 2, Gupta teaches the storage device according to claim 1. Gupta teaches resistive access elements Fig. 7: 15, 15”, 17, 17” between volatile storage unit and non- volatile storage unit being used for writing and restoring operation.
Gupta is silent with respect to “…a variable resistance element connected between the volatile storage unit and the voltage-controlled magneto-resistive effect element, the variable resistance element enabling resistance between the volatile storage unit and the voltage-controlled magneto-resistive effect element to vary”.
HSU teaches -
Memory device (memory device with “S-NVM” cell structure. See e.g., para [0007], para [0013], Fig. 2C-Fig. 2E) further comprising a variable resistance element (Fig. 2C: 213a, 213b transistor switches. These transistors change resistance based on various applied control signal “S1” voltage levels shown in Fig. 2C-Fig. E) connected between the volatile storage unit (Fig. 2C: SRAM CELL) and the voltage-controlled magneto-resistive effect element (Fig. 2C: 210a, 210b employed by magnetic memory elements described in para [0093]),
the variable resistance element enabling resistance between the volatile storage unit and the voltage-controlled magneto-resistive effect element to vary (Fig. 2C-Fig. 2E in context of para [0074]-para [0077]: see various voltage levels of “S1” used during “writing” and “restoring”) .
Both Gupta and HSU are in the same field of endeavor of NVSRAM read/ write operation improvement and they are in analogous field of art. An ordinary skill in the art would understand the use of HSU’s transistor switches into the apparatus of Gupta.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of HSU into the teachings of Gupta such that variable resistance transistor switches can be employed as access element in Gupta’s NVSRAM device to control read/ write current and facilitate read/ write operation in order to reduce data buses (i.e. reduce area) and improve operational speed (see HSU Background).
Regarding claim 3, Gupta and HSU teach the storage device according to claim 2. HSU wherein the variable resistance element varies resistance to cause cell voltages applied to the voltage-controlled magneto-resistive effect element to be substantially equal to each other (Fig. 2C-Fig. 2E: same control signal “S1” and control line used in 213a, 213b which are substantially same transistors and thus they will conduct equal current with equal channel resistance and will impact NV bit cell similarly) ,
the cell voltages being a cell voltage applied when the voltage-controlled magneto-resistive effect element transitions from a high resistance state to a low resistance state and a cell voltage applied when the voltage-controlled magneto-resistive effect element transitions from the low resistance state to the high resistance state (Fig. 2C-Fig. 2E: in context of para [0074]-para [0077]).
Regarding claim 4, Gupta and HSU teach the storage device according to claim 2. HSU teaches wherein the variable resistance element (Fig. 2C-Fig. 2E: 213a, 213b) is a field effect transistor (para [0089], para [0064]) whose on-resistance varies on a basis of a gate voltage (Fig. 2C-Fig. 2E: control signal “S1” applied with VDD for restoring and vset+vt or vinh+vt for writing. Channel resistance of 213a, 213b would vary when different on voltages are applied. See e. g., para [0074]-para [0077]).
Regarding claim 5, Gupta and HSU teach the storage device according to claim 4. HSU teaches wherein the field effect transistor (Fig. 2C-Fig. 2E: 213a, 213b) is used not only as the variable resistance element but also as a storing transistor (storing transistor interpreted as a circuit that facilitates storing data into memory components. See e.g., instant application spec para [0081]) that stores data from the volatile storage unit to the voltage-controlled magneto-resistive effect element and a restoring transistor that restores the data from the voltage-controlled magneto-resistive effect element to the volatile storage unit (Fig. 2C-Fig. 2E in context of para [0074]-para [0077]: 213a, 213b facilitates “writing” data from SRAM to NVM and “restoring” data from NVM to SRAM) .
Regarding claim 6, Gupta and HSU teach the storage device according to claim 4. HSU teaches further comprising a gate voltage switching unit (para [0005], para [0074]: controller generating S1 control signal) that switches between a first gate voltage applied to the field effect transistor in a case where low resistance writing is performed for the voltage-controlled magneto-resistive effect element and a second gate voltage applied to the field effect transistor in a case where high resistance writing is performed for the voltage-controlled magneto-resistive effect element (Fig. 2C, Fig. 2D in context of para [0074]-para [0076]: see writing for set and reset data) .
Regarding claim 8, Gupta and HSU teach the storage device according to claim 6. Gupta teaches further comprising a voltage driver (para [0021], para [0060], Fig. 7: 33, Fig. 7 bit line coupling in combination that generates biasing of VCMA MRAM elements) that applies a reversal voltage (changes in free layer directions) that reverses a magnetization direction of the voltage-controlled magneto-resistive effect element on a basis of a voltage controlled magnetic anisotropy (VCMA) effect (para [0059], para [0060]: VCMA components would follow voltage controlled magnetic anisotropy effect)
Regarding claim 9, Gupta and HSU teach the storage device according to claim 8. Gupta teaches wherein in the voltage-controlled magneto-resistive effect element, a low resistance state and a high resistance state (Fig. 7: 74, 74’ complementary states) according to the data complementarily held in the volatile storage unit (Fig. 7: nodes of SRAM) are each stored on a basis of stepwise change in voltage (in context of para [0074]-para [0077]: varying S1 levels causes 213a, 213b conductivity differences and applied voltage differences on VCMA component) having an identical polarity applied (Fig. 7: resulting same positive potential being applied to VCMA components) to the voltage-controlled magneto-resistive effect element (Fig. 7: 74, 74’ and para [0059], para [0060]: VCMA components).
15. Claim 19 is/are rejected under 35 U.S.C. 103 as being obvious over Gupta et al . (US 2021/0158859 A1), in view of Chuang (US 20150016176 A1).
Regarding claim 19, Gupta and HSU teach 19. The storage device according to claim 1,
Chuang teaches wherein the volatile storage unit is a flip-flop (Fig. 3: 14; see para [0020]: “flip-flop circuit” employed in the memory).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Chuang into the teachings of Gupta and HSU such that flip flop circuit can be employed in the memory apparatus in order to facilitate retention and use of logic/ calculation data from system.
Allowable Subject Matter
Claims 7, and 10-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In addition, any associated 112b rejection must be over-come.
Regarding claims listed above , the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure :
Sugahara (US 2022/0084583 A1): Fig. 1-Fig. 61B are applicable for all claims.
Ahn (US 2010/0202191 A1): Fig. 1A-Fig. 3 applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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