Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20200194393).
Regarding claim 1, Wu discloses a method for manufacturing a multilayer printed circuit board, comprising:
a) assembling at least one first electronic component (component 210, Fig. 16) to an inner conductive layer (the conductive layer having the contact pad 140, Fig. 15) of a printed circuit board (the circuit board in Fig. 16), said assembling including the following operations of:
1) depositing a solder paste (the solder 207, Fig. 16, is a combination of solder, ting and copper; paragraph 49) onto the conductive layer, said solder paste including tin, copper balls and a soldering flux,
2) positioning the electronic component on the solder paste (207), and then
b) depositing a dielectric layer (depositing the redistribution structure 240; Fig. 18) onto the first electronic component and the inner conductive layer; and
c) assembling at least one second electronic component (assembling the semi-finished substrate 300 on top of the layer 240, Fig. 24) to an outer conductive layer (244, Fig. 22) of the printed circuit board, said assembling of the second electronic component including the following operations of:
i. depositing a solder bead (the conductive connector 246 is a solder structure; paragraph 65) onto an outer conductive layer (22),
ii. positioning the second electronic component on the solder bead (Fig. 24).
Wu does not explicitly disclose soldering by diffusion said electronic component; softly soldering the second electronic component, characterized in that the solder bead comprises a tin-based alloy, distinct from the solder paste.
Wu suggests the component 210 is bonded to the contact pad 140 through solder transferring, evaporation, electroplating, printing, ball placement, or the like. It is obvious that Wu was trying to list as many methods as possible to solder a component to a pad.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a common method such as diffusion in order to attach the electronic component to the pad of the circuit board.
Wu further suggests the solder 246 comprising solder, tin, or a combination thereof.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use tin-based alloy in the solder in order to attach the component to the pad of the circuit board.
Regarding claim 2, Wu discloses the claimed invention as set forth in claim 1. Wu further suggests the solder paste comprises a melting temperature and a reflow temperature distinct from each other, the reflow temperature being substantially higher than the melting temperature, and the solder bead comprises a single melting temperature (since the composition of the solder paste and the solder bead are different from each other as discussed in claim 1, it is obvious that the characteristic such as melting temperature and reflow temperature between the solder paste and the solder bead are different from each other).
Regarding claim 5, Wu discloses the claimed invention as set forth in claim 1. Wu further suggests a plurality of steps a) of assembling the first electronic component (assembling component 210) and steps b) of depositing a dielectric layer (deposit layer 240), carried out successively one after the other before the step c) of assembling the second electronic component (assembling substrate 300 on top of layer 240), an inner layer (forming the layers of 240) of the multilayer printed circuit board being formed after each set of a step a) and a step b).
Regarding claim 6, Wu discloses the claimed invention as set forth in claim 1. Wu further suggests multilayer printed circuit board (the circuit board in Fig. 16 or 21) including at least a first and a second electronic component (component 210 and 300) connected to an inner conductive layer (there are inner and outer layers such as 228, 242) and an outer conductive layer respectively, said inner and outer conductive layers being separated from each other by a dielectric layer (there are many dielectric layers such as layer 230), the multilayer printed circuit board being obtained by the manufacturing method according to claim 1.
Allowable Subject Matter
Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 2, a combination of limitations that the reflow temperature of the solder paste is at least 100° C. higher than the melting temperature of said solder paste. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 4, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the step a) of assembling the first electronic component and the step c) of assembling the second electronic component each include an operation of heating the solder bead and the solder paste to a maximum temperature of 260° C. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu (US 20200365525) discloses a circuit board having a buried component, Fig. 19.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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