DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 7,650,585 to Miller et al. (hereafter Miller).
Regarding independent claim 1, Miller teaches an electronic apparatus for detecting or correcting or detecting and correcting at least one datum error in an electronic device or electronic circuit or electronic system comprising:
a controller (FIG. 5: all components of the figure except BRAM_block0, BRAM_block1 and BRAM_block2, which correspond to BRAMs 422, 428 and 434 of FIG. 4B),
a first memory connected with the controller (FIG. 4B: BRAM 428), and having a first data with an error or a number of errors (FIG. 4B: when value on line 440 is different from those on lines 438 and 442, this implies data on BRAM 428 having error(s), see 7:64-9:3), and
a second memory connected with the controller (FIG. 4B: BRAM 422), and having a second data with no error or with a number of errors that is lower than the number of errors in the first memory (i.e. when value on lines 438 and 442 are the same, this implies data on BRAM 422 having no error, see 7:64-9:3), and that is in some fashion related to or resembling the first data (see 4:60-65), and wherein the controller performs the error detection or the error correction or both the error detection and the error correction to the first data by using the second data (see 8:43-9:3).
Regarding dependent claim 2, Miller teaches wherein the second memory is more robust against errors than the first memory (BRAM 422 has no error compared to BRAM 428 with error(s)).
Regarding dependent claim 3, Miller teaches wherein the second memory is more robust from errors than the first memory or the second memory is different from the first memory by one or a combination of the following parameters: physical address on the same integrated circuit die or location in different die, located in another integrated circuit die, having one or more copies of the second data that is some fashion related to or resembling the first data in the first memory, integrated circuit die, data capacity of the first data and the second data, fabrication process, layout including the number or type of ring-guards, interfacing circuit, architecture or topology, transistor configuration, parasitic capacitance, speed or delay, power dissipation, integrated circuit area, operating voltage, Radiation-Hardened-By-Design, or Radiation-Hardened-By-Process (This claim simply implies that information sources A and B store redundant information and are in different locations regardless of memory types).
Regarding dependent claim 4, Miller teaches wherein the controller computes redundancy using the first data or part of the first data and the second data or part of the second data, or only the second data or part of the second data, wherein the redundancy, in an either temporal or spatial fashion, includes one or a combination of the following: i.e. TMR, see 1:45-53).
Regarding dependent claim 5, Miller teaches wherein the first memory or the second memory further have a third data that is in some fashion related to or resembling the first data (FIG. 4A: BRAM 434), wherein the controller performs error detection or error correction or both error detection and error correction to the first data by using the second data, or the third data, or both the second data and the third data (see 8:43-9:3).
Regarding dependent claim 6, Miller further teaches a digital processor wherein the digital processor is a computational device, microprocessor, microcontroller, state-machine, or a field programmable gate array, and the controller is either embedded in the digital processor, its functionality realized by the digital processor, or a separate electronic device or electronic circuit connected to the digital processor (FIG. 1B: processor 104).
Regarding independent claim 7, Miller teaches an electronic apparatus for detecting or correcting or both detecting and correcting at least one datum with error in an electronic device or electronic circuit or electronic system comprising:
a first memory (FIG. 4B: BRAM 428) having a first data with an error or a number of errors (FIG. 4B: when value on line 440 is different from those on lines 438 and 442, this implies data on BRAM 428 having error(s), see 7:64-9:3), and
a second memory (FIG. 4B: BRAM 422) having a second data whose information is either identical to, or in some fashion related to or resembling the first data (see 4:60-65),
wherein the error detection or the error correction or both the error detection and the error correction to the first data is based on using the second data (see 8:43-9:3).
Regarding dependent claim 8, Miller teaches wherein the second memory is more robust against errors than the first memory (BRAM 422 has no error compared to BRAM 428 with error(s)).
Regarding independent claim 21, Miller teaches a method to detect or correct or both detect and correct at least one datum with error in an electronic device or electronic circuit or electronic system comprising:
at least one of detecting an error to a first data in a first memory or correcting the error to the first data in the first memory (FIG. 4B: when value on line 440 is different from those on lines 438 and 442, this implies data on BRAM 428 having error(s), see 7:64-9:3) using a second data stored in a second memory (i.e. when value on lines 438 and 442 are the same, this implies data on BRAM 422 having no error, see 7:64-9:3), wherein the second data of the second memory is either identical to, or in some fashion related to or resembling the first data of the first memory (see 8:43-9:3).
Regarding dependent claim 22, Miller teaches wherein the second memory is more robust against errors than the first memory (BRAM 422 has no error compared to BRAM 428 with error(s)).
Regarding dependent claim 23, Miller teaches wherein the first memory or the second memory further comprises a third data that is in some fashion related to or resembling the first data (FIG. 4B: data on BRAM 434), wherein the at least one of detecting the error to the first data in the first memory or correcting the error to the first data in the first memory is by using the second data, or the third data, or both the second data and the third data (see 8:43-9:3).
Claims 7-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 5,907,671 to Chen et al. (hereafter Chen).
Regarding independent claim 7, Chen teaches an electronic apparatus for detecting or correcting or both detecting and correcting at least one datum with error in an electronic device or electronic circuit or electronic system comprising:
a first memory (FIG. 1: information source A) having a first data with an error or a number of errors (original signal Ai may have error(s), see 3:19-22), and
a second memory (FIG. 1: information source B) having a second data whose information is either identical to, or in some fashion related to or resembling the first data (FIG. 1: information sources A, B and C are redundant sets of information sources, see 1:3-62),
wherein the error detection or the error correction or both the error detection and the error correction to the first data is based on using the second data (see 3:50-62).
Regarding dependent claim 8, Chen teaches wherein the second memory is more robust against errors than the first memory (for example, when information source A has error, and information B does not).
Regarding dependent claim 9, Chen teaches wherein the second memory comprises: a first encoded data or at least a copy of the first encoded data, wherein the first encoded data is in some fashion related to or resembling the first data (FIG. 1: first encoded data is original data Ai, which is related to desired first data Di), or a second encoded data or at least a copy of the second encoded data, wherein the second encoded data is in some fashion related to or resembling the first data, or combination of the first encoded data, the at least a copy of the first encoded data, the second encoded data or the at least a copy of the second encoded data, wherein the first encoded data and the second encoded data are the same or different (FIG. 1: second encoded data is original data Bi, which is related to desired second data Ei), the error detection or the error correction or both the error detection and the error correction to the first data uses one or more of the following: the first encoded data or the at least a copy of the first encoded data, the second encoded data or the at least a copy of the second encoded data, or a combination of the first encoded data, the at least a copy of the first encoded data, the second encoded data, or the at least a copy of the second encoded data (FIG. 1: Ai, Di, Bi, Ei are all related because they are data from redundant sets of information sources).
Regarding dependent claim 10, Chen teaches wherein the first memory or the second memory further comprises a third data that is in some fashion related to or resembling the first data (FIG. 1: Ai and Bi are resembling because they are redundant sets of information sources), and wherein the error detection or the error correction or both the error detection and the error correction to the first data uses the second data, or the third data of the first memory or the third data of the second memory, or both the second data and the third data of the first memory, or the third data of the second memory (FIG. 1: Ai, Di, Bi, Ei are all related because they are data from redundant sets of information sources, see 3:50-62).
Regarding dependent claim 11, Chen teaches wherein the error detection to the first data uses the third data of the first memory or of the second memory, wherein either when an error is detected, the error correction to the first data uses the second data, or otherwise when no error is detected, no error correction is performed to the first data (FIG. 1: Ai, Di, Bi, Ei are all related because they are data from redundant sets of information sources, see 3:50-62).
Regarding dependent claim 12, Chen teaches wherein the first memory further comprises a third encoded data which is in some fashion related to or resembling the first data, the second data comprises one or both of the following: the first encoded data comprising a copy of the third encoded data, or the at least a copy of the first encoded data, and the error detection or the error correction or both the error detection and the error correction to the first data by using the third encoded data, and either the first encoded data, the at least a copy of the first encoded data or combination of the first encoded data or the at least a copy of the first encoded data (FIG. 1: Ai, Di, Bi, Ei are all related because they are data from redundant sets of information sources, see 3:50-62).
Regarding dependent claim 13, Chen teaches wherein the first encoded data or the second encoded data or both the first and second encoded data is encoded by one or more of the following combinations: parity, Hamming, cyclic, or hash function (FIG. 1: parity for parity check in element 20).
Regarding dependent claim 14, Chen implicitly teaches wherein the error in the datum of the first memory is due to a fault by either one or more of the following combinations: during the writing into the address of the memory location that would store the datum or data, an erroneous change of the datum or data during storage, or during the reading of the address of the memory location that embodies the datum or data (it is obvious that the error in the datum is caused by read and write operations and flipping of data during storage).
Regarding dependent claim 15, Chen teaches wherein for the first data and the second data, the data capacity or the number of bits of the second data is either the same or different from the data capacity or the number of bits of the first data and they have different addresses in the same memory integrated circuit die, or are in physically different memory integrated circuit dies (this claim does not particularly impose a limit on physical locations of information sources A and B of Chen).
Regarding dependent claim 16, Chen teaches wherein the first data comprises at least a memory bit, and the second data comprises either one or both the at least memory bit, or at least an encoded bit that is in some fashion related to or resembling the first data (FIG. 1: Ai, Di, Bi, Ei are all related because they are data from redundant sets of information sources, see 3:50-62).
Regarding dependent claim 17, Chen teaches wherein the third data of the first memory or of the second memory or of both the first and second memories comprises at least a bit encoded by one or more of the following combinations: parity, Hamming, cyclic, or hash function (FIG. 1: parity for parity check in element 20).
Regarding dependent claim 18, Chen teaches wherein the second memory is more robust from errors than the first memory or the second memory is different from the first memory by one or a combination of the following parameters: physical address on the same integrated circuit die or location in different die having one or more copies of the second data that is some fashion related to or resembling the first data in the first memory, integrated circuit die, data capacity of the first data and the second data, fabrication process, layout including the number or type of ring-guards, interfacing circuit, architecture or topology, transistor configuration, parasitic capacitance, speed or delay, power dissipation, integrated circuit area, operating voltage, Radiation-Hardened-By-Design, or Radiation-Hardened-By-Process (This claim simply implies that information sources A and B store redundant information and are in different locations regardless of memory types).
Regarding dependent claim 19, Chen teaches wherein the error detection or the error correction or both the error detection and the error correction involves an encoding operation, a decoding operation or both an encoding and a decoding operation, wherein during the encoding operation, the first data to be written is encoded as an encoded data that provides data integrity information, the first data is written into the first memory, the encoded data is written as the second data into the second memory, and wherein during the decoding operation, the first data in the first memory is read, the second data in the second memory is read and decoded, and if there is a discrepancy between the read first data and the read-and-decoded second data, the read first data is corrected by using the read-and-decoded second data (FIG. 1: the process of obtaining desired first and second data Di and Ei from original data Ai and Bi is seen as including decoding operations using parity bit b stored in information sources A and B, respectively).
Regarding dependent claim 20, Chen teaches wherein the error detection or the error correction or both the error detection and the error correction involves an encoding operation, a decoding operation or both an encoding and a decoding operation, wherein during the encoding operation, the first data to be written is encoded as two encoded data that provide data integrity information, the first data is written into the first memory, one of the two encoded data is written as the second data into the second memory, the other one of the two encoded data is written as the third data in the first memory or in the second memory, and during the decoding operation, the first data in the first memory is read, the second data in the second memory is read and decoded, the third data in the first memory or in the second memory is read and decoded, and if there is a discrepancy between the read first data and either the read-and-decoded second data or the read-and-decoded third data, the read first data is corrected by using the read-and-decoded second data from the second memory, the read-and-decoded third data, or both the read-and-decoded second and the third data (FIG. 1: the process of obtaining desired first and second data Di and Ei from original data Ai and Bi is seen as including decoding operations using parity bit b stored in information sources A and B, respectively).
Regarding independent claim 21, Chen teaches a method to detect or correct or both detect and correct at least one datum with error in an electronic device or electronic circuit or electronic system comprising:
at least one of detecting an error to a first data in a first memory or correcting the error to the first data in the first memory (FIG. 1: original signal Ai from information source A may have error(s), see 3:19-22) using a second data stored in a second memory (FIG. 1: using Bi and Ei, see 3:50-62), wherein the second data of the second memory is either identical to, or in some fashion related to or resembling the first data of the first memory (FIG. 1: information sources A, B and C are redundant sets of information sources, see 1:3-62).
Regarding dependent claim 22, Chen teaches wherein the second memory is more robust against errors than the first memory (for example, when information source A has error, and information B does not).
Regarding dependent claim 23, Chen teaches wherein the first memory or the second memory further comprises a third data that is in some fashion related to or resembling the first data (FIG. 1: Ci and Fi of information source C), wherein the at least one of detecting the error to the first data in the first memory or correcting the error to the first data in the first memory is by using the second data, or the third data, or both the second data and the third data (see 3:19-22).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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September 22, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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