Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 11 and 18.
b. Claims 1-20 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 02/19/2025. The changes and remarks disclosed therein were considered.
An amendment of the specification and the drawing has been amended. Therefore, claims 1-20 are pending in the application.
Drawings
3. The drawings were received on 02/19/2025 and 12/23/2024. These drawings are review and accepted by examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims are 1-2 and 18 rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0343343 A1 to Teague et al. (hereafter Teague et al).
Regarding Independent Claim 1, Teague et al in Figures 1-9 are directly discloses a compute-in-memory (CIM) circuit (a computer device 100, Fig. 1) comprising:
a first number (M) of computing cells (a CIM array 101(1) and CIM arra y (2), Fig. 1, CIM 201, Fig. 2, array 306, Fig. 3), wherein each of the M computing cells (the CIM array 306 includes a plurality of memory cells 314(1)(1)….314 (c)(r), Fig. 3) comprises a second number (N) of stages which, when collectively performed, are configured to provide at least one multiply-accumulate (MAC) result of a respective plurality of input data elements and a respective plurality of weight data elements (for example, the CIM array 306 comprises c column and r rows of CIM cells 314(1)(1)-314 (c)(f) wherein each CIM cell 314(i)(j) is configured to store a corresponding weight value and multiply it with a received input value, paragraph 0035); and
a global CIM controller (a memory module controller 103, Fig. 1) operatively coupled to the M computing cells (the CIM array 306 includes a plurality of memory cells 314(1)(1)….314 (c)(r), Fig. 3) and is configured to schedule a first one of the N stages of a first one of the M computing cells and a first one of the N stages of a second one of the M computing cells to be simultaneously performed, based on identifying that a first peak current previously consumed by the first stage of the first computing cell (the CIM array 105(1)) and a second peak current previously consumed by the first stage of the second computing cell are different (the CIM array 101(2))(for example, the memory module controller 103 for controlling the operation of the memory CIM array 101(1) and 101(2) as the separate stage, Fig. 1, paragraph 0018-0019. Also, the CIM cells 314 (1)(1)-314 (c)(f) provided as an input to corresponding ADC 308 (1)-308 (c) and receive a reference voltage VREF is simply a comparator that compare the value on the corresponding bitline 312 in the ADC module 304, Fig. 3, paragraph 0025-0026 and the related disclosures).
Regarding dependent Claim 2, Teague et al in Figures 1-9 are directly discloses a compute-in-memory (CIM) circuit (a computer device 100, Fig. 1) wherein the first peak current is higher than the second peak current the CIM cells 314 (1)(1)-314 (c)(f) provided as an input to corresponding ADC 308 (1)-308 (c) and receive a reference voltage VREF is simply a comparator that compare the value on the corresponding bitline 312 in the ADC module 304, Fig. 3, paragraph 0025-0026).
Regarding claim 18, they encompass the same scope of invention as that of claims 1-2, except they draft the invention in method format instead of apparatus format. Teague et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claim 18, are therefore rejected in method format for the same reasons claims 1-2, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
5. Claims 3-10 and 19-20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 3-4, the prior art fails to tech or suggest the claimed limitations, namely, the global CIM controller is further configured to schedule the first stage of the first computing cell, the first stage of the second computing cell, and a first one of the N stages of a third one of the M computing cells to be simultaneously performed, based on identifying that the first peak current, the second peak current, and a third peak current associated with the first stage of the third computing cell are different, wherein the first peak current is higher than any of the second peak current or the third peak current.
With respected to dependent claim 5, the prior art fails to tech or suggest the claimed limitations, namely, a maximum peak current consumed by the M computing cells is equal to a sum of respective peak currents of the N stages.
With respected to dependent claim 6, the prior art fails to tech or suggest the claimed limitations, namely, the N stages performed by each of the M computing cells each include one or more multiplication operations, one or more accumulation operations, one or more subtraction operations, and one or more alignment operations.
With respected to dependent claims 7-10, the prior art fails to tech or suggest the claimed limitations, namely, each of the M computing cells further comprises a respective local CIM controller configured to schedule a write operation based on a delayed write enable signal, the write operation including writing the respective weight data elements into a respective memory array, wherein each of the M computing cells is configured to simultaneously perform one of its N stages and the write operation, based on the delayed write enable signal.
With respected to dependent claim 19, the prior art fails to tech or suggest the claimed limitations, namely, the first stage and the second stage each include one or more multiplication operations, one or more accumulation operations, one or more subtraction operations, and one or more alignment operations.
With respected to dependent claim 20, the prior art fails to tech or suggest the claimed limitations, namely, further comprising: generating a first partial multiply-accumulate (MAC) result by performing a plurality of the first stages; and generating a second partial MAC result by performing a plurality of the second stages.
6. Claims 11-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 11: there is no teaching, suggestion, or motivation for combination in the prior art to “a global CIM controller operatively coupled to the computing cells, and is configured to shift a first one of the stages of a second one of the computing cells to align with a first one of the stages of a first one of the computing cells, based on identifying that a first peak current previously consumed by the first stage of the first computing cell is higher than a second peak current previously consumed by the first stage of the second computing cell.” in a compute-in-memory (CIM) circuit as claimed in the independent claim 11. Claims 12-17 are also allowed because of their dependency on claim 11.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al (US. 2020/0105337 A1) discloses memory cells and array for compute in memory computations.
Happ et al (US. 2009/0003034 A1) discloses multiple write configuration for a memory cell.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights