DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9-13 and 16-20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
For claims 9, 11-13, 16, and 18-20, the term “all daemons” and “the daemons” contradict each other and lack sufficient antecedent basis in the claim. “all daemons” suggests there are multiple daemons in the system, which could be grouped in multiple ways. Referring to “the daemons” is indefinite because it is unclear to which group of the “all daemons” the claim refers to. It is suggested claim 9 be amended to “[[all]] a plurality of daemons”
For claim 17, the term “the verification” (two instances in the claim) lacks sufficient antecedent basis in the claim. It is suggested that first instance in claim 17 be amended to “[[the]] a verification”.
Dependent claims inherit rejections.
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Claims 10-12 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and all 35 USC § 112, rejections are overcome.
Reasons for Allowability
For dependent claims 2-8, 10-12, and 15-20,
Claim 2 is allowable because although prior art has been found to teach refusing the boot if the authentication failed, no prior art was found to teach recording the identification on a separate list, as it pertains to the other portions of the claim, in a manner that would motivate a person of ordinary skill in the art to combine it as an obvious inclusion. Claims 3-8 depend on claim 2. Claims 10-12 are allowed for similar reasons. Claims 10-12 are a method. Claims 15-20 are allowable for similar methods.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gu (US 2025/0130965 A1), and further in view of Pennell (US 2025/0045401 A1).
For claim 1,
Gu teaches a server system, comprising: a management circuit, comprising: a first control circuit comprising a storage unit and firmware, wherein the storage unit is configured to store [], and the firmware comprises a plurality of daemons (see figure 1A, paragraph [0020]: view block 100 as said server system including servers/sleds/blades 105x; view Baseboard Management Controller (BMC) 110x as said management circuit; see figures 2-3, [0013], [0015], [0061]: BMC includes firmware which includes Daemons; the firmware is stored in storage of the BMC; view underlying hardware of block 230 that supports storage as said first circuit); a second control circuit coupled to the first control circuit (see figure 2: view underlying hardware of block 230 that supports interface 253 as said second circuit); and a first memory coupled to the first control circuit (see figure 2: view block 230e and any other memory not shown but is there in support of processors as said memory), wherein the first memory is configured to store a first verification value (see [0053]: verification includes verification values); and a processing circuit coupled to the management circuit, comprising: a second memory coupled to the first control circuit (see figures 1A, 2: view the Information handling System (IHS) that includes processors, memory, and storage as said processing circuit), []; and a power control circuit coupled to the second control circuit and a power supply (see figures 1-2: view block 220 as said power control and block 136 as said power supply); [], the first control circuit provides a first signal to the second control circuit, the second control circuit provides a startup signal to the power control circuit based on the first signal, the power control circuit controls the power supply to supply power to the processing circuit based on the startup signal to start the processing circuit (see [0002] and other locations: being able to cycle power and reset IHS by BMC is a standard BMC functionality; view reset and cycling power to power supply as said startup signal), and when the processing circuit starts normally and all the daemons operate normally after the processing circuit starts, the first control circuit stores the processing circuit identification information in the first list (this always occurs, as it is standard BMC operation, specified in the “BMC documentation” website (provided below): each specific CPU has its own license agreement and associated authorization password; view that as said processing identification information; also, view successful boot, which normally occurs as said firmware/daemons and CPU running normally after start; boot always precedes dependent processes such as authentication) and “store a first list” and “store processing circuit identification information” (all/list of processors IDs/passwords are stored in BMC memory, in accordance with the license agreement)
Gu does not explicitly teach and “wherein the second memory is configured to store a second verification value” and “wherein the first control circuit is configured to compare the first verification value and the second verification value to verify the processing circuit, when the processing circuit passes verification”
However, Pennell teaches and “wherein the second memory is configured to store a second verification value” and “wherein the first control circuit is configured to compare the first verification value and the second verification value to verify the processing circuit, when the processing circuit passes verification” (see [0007-0008] and other locations: authentication includes comparing verification values for each BMC and motherboard)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gu to include “wherein … passes verification”, as taught by Pennell, because each one of Gu and Pennell teach communication between mother board and openBMC therefore they are analogous arts and because openBMC is more prone to hacking (see [0007-0008] and other locations).
For claim 9,
The claim recites essentially similar limitations as claim 1; claim 9 is a circuit verification method.
For claim 13,
The combination of Gu and Pennell teaches the limitations of claim 9 for the reasons above.
Gu further teaches wherein the server system further comprises a display device (see [0036] and other locations), and the circuit verification method further comprises: when the processing circuit fails the verification, and when the processing circuit fails to start normally or when the daemons exhibit abnormal operation after the processing circuit starts, the first control circuit displaying an error message on the display device (see [0002]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gu (US 2025/0130965 A1).
For claim 14, Gu teaches a circuit verification method for a server system, wherein the server system comprises a management circuit and a processing circuit, the processing circuit is coupled to the management circuit, the management circuit comprises a first control circuit, a second control circuit, and a first memory, the first control circuit comprises a storage unit and firmware, the second control circuit is coupled to the first control circuit, the processing circuit comprises a second memory and a power control circuit, the second memory is coupled to the first control circuit, the power control circuit is coupled to the second control circuit, and the circuit verification method comprises: (see rejections pointed to in claim 1: see figure 1A, paragraph [0020]: view block 100 as said server system including servers/sleds/blades 105x; view Baseboard Management Controller (BMC) 110x as said management circuit; see figures 2-3, [0013], [0015], [0061]: BMC includes firmware which includes Daemons; the firmware is stored in storage of the BMC; view underlying hardware of block 230 that supports storage as said first circuit; see figure 2: view underlying hardware of block 230 that supports interface 253 as said second circuit; see figure 2: view block 230e and any other memory not shown but is there in support of processors as said memory; see [0053]: verification includes verification values; see figures 1A, 2: view the Information handling System (IHS) that includes processors, memory, and storage as said processing circuit; see figures 1-2: view block 220 as said power control and block 136 as said power supply); the first control circuit checking whether processing circuit identification information stored in the second memory has been stored in a first list or a second list stored in the storage unit (BMC documentation/specification teaches that the passwords of authenticated processors stored in BMC are continuously searched/ looked up; view that as checking; view memory addresses ranges storing these passwords as said lists); and when the processing circuit identification information has been stored in the first list, the first control circuit providing a first signal to the second control circuit, the second control circuit providing a startup signal to the power control circuit based on the first signal, and the power control circuit controlling a power source to supply power to the processing circuit based on the startup signal to start the processing circuit (see rejection to claim 1: (see [0002] and other locations: being able to cycle power and reset IHS by BMC is a standard BMC functionality; view reset and cycling power to power supply as said startup signal)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
“Overview of BMC product software authorization” from BMC documentation website to provide support on what occurs once processor is authenticated.
“Statements in a DASD MANAGER PLUS job” from BMC documentation website to provide support these passwords are often searched
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIR LEIBOVICH whose telephone number is (571)270-3796. The examiner can normally be reached 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114