DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, Claims 1-8, 11-15, 18-19 in the reply filed on 07/20/26 is acknowledged. Claims 9-10 and 16-17 are withdrawn. The traversal is on the ground(s) that the examiner did not show it will be a serious burden. This is not found persuasive because having multiple species in one application and using different queries for search is shown.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 11-15, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 20220021831 A1; hereafter Jin) in view of Mouli et al. (US 20040092054 A1; hereafter Mouli).
As of Claim 1: Jin teaches FIGS. 2A and 2B, an image sensing device (¶0003 exhibit ToF) comprising: a semiconductor substrate; a plurality of unit pixels supported by the semiconductor substrate (¶0060 and note that semiconductor substrate 10) and arranged in a first direction and a second direction intersecting the first direction to form a pixel array (¶¶0085-0086 and note that pixel array 110), each unit pixel including a photoelectric conversion element configured to convert light incident to the photoelectric conversion element into photocharges (¶¶0070,0075 and note that the plurality of demodulation transfer gates TGA and TGB may transfer a photo charge collected by the common photogate CPG to the plurality of floating diffusion regions FDA and FDB), and a plurality of floating diffusion regions disposed over the photoelectric conversion element to receive and store the photocharges (¶¶0045-0050 and note that FIGS. 4 and 5, the depth pixel PX may further include a plurality of charge storing structures respectively disposed in the peripheral region PREG between the plurality of floating diffusion regions FDA and FDB and the plurality of demodulation transfer gates TGA and TGB. The plurality of charge storing structures may temporarily store the photo charge transferred from the common photogate CPG before transferring the photo charge to the plurality of floating diffusion regions FDA and FDB.).
Mouli is a similar or analogous system to the claimed invention as evidenced Mouli teaches isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels that would have prompted a predictable variation of Jin by applying Mouli’s known principal of a plurality of transfer gates supported by the semiconductor substrate and disposed between adjacent unit pixels, and configured to isolate the adjacent unit pixels from each other and to transfer the photocharges generated by the photoelectric conversion element to the plurality of floating diffusion regions (¶¶0032-0035, 0042 and note that FIGS. 3A and 3B. A 2.times.2 CMOS image sensor pixel array is shown in FIG. 3A to better illustrate the invention. In accordance with the second embodiment of the invention, a region rich in positively charged holes is created along the STI sidewall 229 by providing an isolation gate 270 over the trench isolation region 228 and surrounding the p-n-p junction region 221. The isolation gate 270 is preferably provided slightly over an electrical connection region 223. The isolation gate 270 is also preferably formed to extend around the p-n-p junction region 221 to a gate, for example, transfer gate 250, but does not contact the transfer gate, so as not to short the gates. The isolation gate 270 has a length L.sub.x in the x-direction and length L.sub.y in the y-direction as shown in FIG. 3A, each of which can be modified to optimize isolation. For example, the length L.sub.x and L.sub.y of the isolation gate 270 may be independently increased or decreased to minimize dark current and cross-talk between adjacent pixels. The isolation gate 270 preferably does not extend around the floating diffusion region 225. Preferably, the isolation gate 270 extends between pixels 200, as indicated by reference numeral 270').
In view of the motivations such as providing an isolation technique that prevents current generation or current leakage as disclosed in ¶0009 of Mouli thereby further improving charge transfer efficiency and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Jin.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
As of Claim 2: Jin in view of Mouli further teaches each of the plurality of transfer gates has a horizontal cross-section of a rectangular shape, and corner regions of adjacent transfer gates arranged in a diagonal direction that is between the first direction and the second direction are in contact with each other (Jin ¶¶0007,0134,0137,0149 and note that FIGS. 19A, 19B and 19C, the shape of the common photo gate CPG may be variously determined. According to the shape of the common photo gate CPG, the first and second demodulation transfer gates TGA and TGB and the overflow gates OG may be disposed in an arrangement to have the symmetric structure).
As of Claim 3: Jin in view of Mouli further teaches the plurality of transfer gates is formed to penetrate the semiconductor substrate (Jin ¶¶0051, 0052,0067,0070 and note that each of the transistors TMA, TMB, TS, TT and TRS may include a gate disposed above a semiconductor substrate and source and drain regions disposed at both sides of the gate in the semiconductor substrate. The gates of the transistors TMA, TMB, TS, TT and TRS correspond to a first demodulation transfer gate TGA, a second demodulation transfer gate TGB, storage gates SG, and floating diffusion (FD) transfer gates TG and reset gates RG, respectively.).
As of Claim 11: Jin in view of Mouli further teaches one of the plurality of unit pixels is surrounded by four transfer gates that are connected to each other and isolated from an adjacent unit pixel, the four transfer gates having corner regions being in contact with each other (Jin ¶¶00 and note that FIGS. 30A, 30B, 30C, 31A, 31B and 31C, each of depth pixels PX51˜PX56 may include a common photo gate CPG disposed adjacent to an upper surface 11 of the semiconductor substrate SUB and a plurality of demodulation transfer gates TGA and TGB having the symmetric structure.).
As of Claim 12: Jin teaches FIGS. 2A and 2B an image sensing device (¶0003 exhibit ToF) comprising: a plurality of unit pixels, each unit pixel including a photoelectric conversion element configured to generate photocharges through photoelectric conversion of incident light and a plurality of floating diffusion regions configured to receive the photocharges and store the received photocharges (¶¶0070,0075 and note that the plurality of demodulation transfer gates TGA and TGB may transfer a photo charge collected by the common photogate CPG to the plurality of floating diffusion regions FDA and FDB); and the plurality of transfer gates configured to transfer the photocharges generated by the photoelectric conversion element to the plurality of floating diffusion regions based on a plurality of demodulation control signals having different phases from one another (¶¶0045-0050 and note that Referring to FIGS. 1, 2A, 2B, 3A and 3B, a depth pixel PX may include a common photogate CPG, a plurality of floating diffusion regions FDA and FDB, a plurality of demodulation transfer gates TGA and TGB, and a plurality of overflow gates OG1 and OG2. FIGS. 1, 2A, 2B, 3A and 3B illustrate two floating diffusion regions FDA and FDB and two demodulation transfer gates TGA and TGB corresponding to a two-tap structure for convenience of illustration. However, the number of the floating diffusion regions and the demodulation transfer gates may be varied in embodiments depending on the number of taps of the depth pixel. In addition, the number of the overflow gates may be variously determined).
Mouli is a similar or analogous system to the claimed invention as evidenced Mouli teaches isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels that would have prompted a predictable variation of Jin by applying Mouli’s known principal of a plurality of transfer gates disposed in a substrate and surrounding each of the plurality of unit pixels and isolating each unit pixel from adjacent unit pixels (¶¶0032-0035, 0042 and note that FIGS. 3A and 3B. A 2.times.2 CMOS image sensor pixel array is shown in FIG. 3A to better illustrate the invention. In accordance with the second embodiment of the invention, a region rich in positively charged holes is created along the STI sidewall 229 by providing an isolation gate 270 over the trench isolation region 228 and surrounding the p-n-p junction region 221. The isolation gate 270 is preferably provided slightly over an electrical connection region 223. The isolation gate 270 is also preferably formed to extend around the p-n-p junction region 221 to a gate, for example, transfer gate 250, but does not contact the transfer gate, so as not to short the gates. The isolation gate 270 has a length L.sub.x in the x-direction and length L.sub.y in the y-direction as shown in FIG. 3A, each of which can be modified to optimize isolation. For example, the length L.sub.x and L.sub.y of the isolation gate 270 may be independently increased or decreased to minimize dark current and cross-talk between adjacent pixels. The isolation gate 270 preferably does not extend around the floating diffusion region 225. Preferably, the isolation gate 270 extends between pixels 200, as indicated by reference numeral 270').
In view of the motivations such as providing an isolation technique that prevents current generation or current leakage as disclosed in ¶0009 of Mouli thereby further improving charge transfer efficiency and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Jin.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
As of Claim 13: Jin in view of Mouli further teaches each of the plurality of transfer gates and each of the plurality of unit pixels have square shapes with a same horizontal cross-sectional area (Jin ¶¶0007,0134,0137,0149 and note that FIGS. 19A, 19B and 19C, the shape of the common photo gate CPG may be variously determined. According to the shape of the common photo gate CPG, the first and second demodulation transfer gates TGA and TGB and the overflow gates OG may be disposed in an arrangement to have the symmetric structure).
As of Claim 14: Jin in view of Mouli further teaches the plurality of floating diffusion regions is located in two corner regions facing each other among four corner regions of each of the plurality of unit pixels (Jin ¶¶00 and note that FIGS. 30A, 30B, 30C, 31A, 31B and 31C, each of depth pixels PX51˜PX56 may include a common photo gate CPG disposed adjacent to an upper surface 11 of the semiconductor substrate SUB and a plurality of demodulation transfer gates TGA and TGB having the symmetric structure.).
As of Claim 15: Jin in view of Mouli further teaches the plurality of floating diffusion regions is located at side surfaces of each of the plurality of unit pixels (Jin ¶¶0045-0049 and note that FIGS. 4 and 5, the depth pixel PX may further include a plurality of charge storing structures respectively disposed in the peripheral region PREG between the plurality of floating diffusion regions FDA and FDB and the plurality of demodulation transfer gates TGA and TGB. The plurality of charge storing structures may temporarily store the photo charge transferred from the common photogate CPG before transferring the photo charge to the plurality of floating diffusion regions FDA and FDB.).
As of Claim 18: Jin in view of Mouli further teaches corner regions of the plurality of transfer gates are connected to each other and sides of the plurality of transfer gates parallel to a long-axis are in contact with the unit pixel, when viewed in a plane (Jin ¶¶ 0072,0080, 0119 and note that FIG. 14, the one common photo gate CPG may be disposed in the center region of the depth pixel PX2 and the demodulation transfer gates TGA, TGB, TGC and TGD and the overflow gates OG1 and OG2 may form a symmetric structure with respect to the common photo gate CPG. The demodulation transfer gates TGA, TGB, TGC and TGD may be symmetric with respect to each of the horizontal line HLX and the vertical line HLY, that is, symmetric with respect to the center CP of the depth pixel PX2. In addition, the overflow gates OG1 and OG2 may be symmetric with respect to each of the horizontal line HLX and the vertical line HLY, that is, symmetric with respect to the center CP of the depth pixel PX2. ).
As of Claim 19: Jin in view of Mouli further teaches the plurality of transfer gates is formed to penetrate the substrate (Jin ¶¶ 0051,0052,0067, 0114 and note that each of the transistors TMA, TMB, TS, TT and TRS may include a gate disposed above a semiconductor substrate and source and drain regions disposed at both sides of the gate in the semiconductor substrate. The gates of the transistors TMA, TMB, TS, TT and TRS correspond to a first demodulation transfer gate TGA, a second demodulation transfer gate TGB, storage gates SG, and floating diffusion (FD) transfer gates TG and reset gates RG, respectively).
Allowable Subject Matter
Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
As of Claim 4: the prior art of record fails to teach or fairly suggest the limitations of claim 4, in combination with claims 1&2, that includes. “the plurality of transfer gates includes: a first transfer gate formed to be in contact with a first side surface of a unit pixel; a second transfer gate formed to be in contact with a second side surface facing or opposite to the first side surface; a third transfer gate formed to be in contact with a third side surface that meets each of the first side surface and the second side surface, and configured to have corners that are in contact with a corner of the first transfer gate and a corner of the second transfer gate; a fourth transfer gate formed to be in contact with a fourth side surface facing or opposite to the third side surface, and configured to have corners that are in contact with a corner of the first transfer gate and a corner of the second transfer gate. ”.
As of Claims 5-8: claims 5-8 are objected as allowable subject matter as well based on the claims dependence on claim 4.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEKONNEN D DAGNEW whose telephone number is (571)270-5092. The examiner can normally be reached on 8:00AM-5:00PM M-Th.
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/MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638
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