Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 10, and 16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Birk (Patent Application Publication 2002/0181306).
Claim 1. A device, comprising: a memory device configured to (configured to is functional language) store a plurality of bits (multilevel DRAM storing multiple bits per cell, Birk [00011, 0021]); a reading device coupled to the memory device at a first node (sense amplifiers 120 and 120’ coupled to the memory through bitlines BL/BR, Birk Fig 2-3 [0038-0042]); and a feedback device configured to (configured to is functional language) adjust the reading device based on a first voltage signal generated at the first node (feedback signal FBK feeds sensed bit information from BL to magnitude sense amplifier 120’ and selectively turns on N8’ and N5’, changing the switching threshold, Birk Fig 3 [0042]), wherein the first voltage signal is generated based on the plurality of bits (the memory cell store two bits using on of four voltage levels and the bitline signal represents the stored multilevel state, Birk [0011, 0041-0042]).
Claim 9. A device, comprising: a memory device (multilevel DRAM storing multiple bits per cell, Birk [00011, 0021]); a first reading circuit coupled to the memory device, and configured to (configured to is functional language) generate a first voltage signal based on data stored in the memory device (sense amplifiers 120 and 120’ coupled to the memory through bitlines BL/BR, voltage state corresponds to the multilevel data stored in the selected memory cell, Birk Fig 2-3 [0038-0042]); and a feedback device configured to (configured to is functional language) adjust the first reading circuit based on the first voltage signal (feedback signal FBK passes sensed bit information to magnitude sense amplifier 120’ and selectively turns on N8’ and N5’, changing its sensing threshold, Birk Fig 3 [0042]).
Claim 10. The device of claim 9, further comprising: a sensing device configured to (configured to is functional language) generate a first digital signal according to the first voltage signal (left side sense amplifier 120 sensed the sign-bit state appearing on the bitline, Birk Fig 3 [0041-0042]), wherein a bit value of the first digital signal is same as a most significant bit of the data (The first portion of Birk’s sensing operation determines the sign bit before the magnitude bit is sensed. The sign bit is the higher order bit of a two bit representation, Birk [0041-0042]).
Claim 16. A method, comprising: generating a first voltage signal at a first node according to data (a stored multilevel cell places a voltage corresponding to its stored state onto the selected bitline during sensing, Birk Fig 3 [0041-0042]); generating a first control signal based on the first voltage signal (the initially sensed sign bit state produced the feedback information through FBK, Birk [0042]); receiving the first control signal by a reading device (magnitude sense amplifier 120’ received the sign-bit feedback through F2, selectively turning on N8’ and N5’, Birk Fig 3 [0042]); and generating, corresponding to the data, a second voltage signal at the first node by the reading device (after the feedback changes the magnitude sense amplifier threshold, the magnitude portion of the stored multilevel state is sensed using that adjusted threshold, Birk [0042-0043]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6, 8, 11, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Birk (Patent Application Publication 2002/0181306) in view of Siau (Patent Application Publication 2016/0254048).
Claim 2. Birk teaches the device of claim 1, but is silent with respect to wherein the reading device comprises: a first switch coupled to the first node; and a second switch configured to control of the first switch according to a first control signal, wherein the feedback device is configured to generate the first control signal based on the first voltage signal.
Siau teaches a first switch coupled to the first node (source follower transistor 534 has its source connected to the bitline, Siau Fig 5F); and a second switch configured to (configured to is functional language) control of the first switch according to a first control signal (transistor 533 controls the gate of source follower transistor 534, Siau Fig 5F), wherein the feedback device is configured to (configured to is functional language) generate the first control signal based on the first voltage signal (the gate bias condition of the precharge transistor is established based on feedback from the bitline voltage, Siau Fig 5F) for the purpose of allowing a selected bitline to be biased to a desired read voltage despite variations in cell characteristics (feedback controlled biasing maintains the selected bitline at the desired read voltage despite variation in cell current voltage behavior of different memory cells, Siau Fig 5B-5F).
Since Birk and Siau are both from the same field of endeavor (semiconductor memory comprising sense amplifiers), the purpose disclosed by Siau would have been recognized in the pertinent art of Birk.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Siau’s transistor controlled feedback biased read circuitry in the circuit taught by Birk for the purpose of establishing and regulating desired bitline read voltages despite variations in memory cell characteristics.
Claim 3. The device of claim 2, wherein the reading device further comprises: a third switch configured to (configured to is functional language) provide a reference voltage signal to a control terminal of the first switch according to the first control signal (feedback source transistor circuit provides the bias read voltage condition to the gate of the bitline driving transistor according to bitline feedback, Siau Fig 5B-5C), the first switch is configured to (configured to is functional language) provide the reference voltage signal to the first node (the source follower transistor precharges the selected bitline to the read voltage, Siau Figs 5B-C).
Claim 4. The device of claim 2, wherein the reading device further comprises: a third switch coupled to the first node (additional transistor controlled sensing precharge path associated with the selected bitline, Siau Fig 5B-5F); and a fourth switch configured to (configured to is functional language) control of the third switch according to a second control signal (corresponding feedback transistor controls the associated bitline driving transistor, Siau Fig 5F), wherein the feedback device is configured to (configured to is functional language) generate the first control signal based on the first voltage signal (the first bias control signal is generated using feedback from the first bitline source node, Siau Fig 5B-5F).
Claim 5. The device of claim 4, wherein the feedback device comprises: a first logic unit configured to (configured to is functional language) receive a reference voltage signal to generate the first control signal (first feedback control path received the read source voltage condition and generated the first gate bias control condition, Siau Fig 5F); and a second logic unit configured to (configured to is functional language) receive the reference voltage signal to generate the second control signal (second feedback control path receives the read source voltage condition and generated the second gate bias control condition, Siau Fig 5F).
Claim 6. The device of claim 5, wherein the reading device further comprises: a fifth switch configured to (configured to is functional language) provide the reference voltage signal to a control terminal of the first switch according to the second control signal (controlled feedback transistor circuitry supplied the vias read voltage condition to the gate of the bitline driving transistor according to the generated control state, Siau Figs 5C-5F).
Claim 8. The device of claim 6, wherein each of the third switch and the fifth switch has a first conductive type (MOS feedback control transistors used in the sensing circuity, Birk Fig 2 Siau Fig 5B-5F), and the first switch has a second conductive type different from the first conductive type (Birk teaches complementary P and N channel transistors in the sense amp Birk Fig 2 [0036-0037]).
Claim 11. Birk discloses the device of claim 9, further comprising: but is silent with respect to a second reading circuit coupled between the first reading circuit and the memory device, and configured to (configured to is functional language) generate the first voltage signal with the first reading circuit, wherein the feedback device is further configured to (configured to is functional language) adjust the second reading circuit based on the first voltage signal.
Siau teaches a second reading circuit coupled between the first reading circuit and the memory device (second sensing read circuit coupled to the memory bitline), and configured to (configured to is functional language) generate the first voltage signal with the first reading circuit (sensing circuit cooperated with the sense amplifier to establish and sense bitline voltages), wherein the feedback device is further configured to (configured to is functional language) adjust the second reading circuit based on the first voltage signal (feedback adjusts the sensing path, Siau Fig 5E-5F) for the purpose of allowing a selected bitline to be biased to a desired read voltage despite variations in cell characteristics (feedback controlled biasing maintains the selected bitline at the desired read voltage despite variation in cell current voltage behavior of different memory cells, Siau Fig 5B-5F).
Since Birk and Siau are both from the same field of endeavor (semiconductor memory comprising sense amplifiers), the purpose disclosed by Siau would have been recognized in the pertinent art of Birk.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Siau’s transistor controlled feedback biased read circuitry in the circuit taught by Birk for the purpose of establishing and regulating desired bitline read voltages despite variations in memory cell characteristics.
Claim 17.Birk teaches the method of claim 16, but is silent with respect to further comprising: providing a first reference voltage signal to a second node according to the by a first switch; and providing the first reference voltage signal to the first node by a second switch, wherein a control terminal of the second switch is coupled to the second node.
Siau teaches providing a first reference voltage signal to a second node according to the by a first switch (first reference bias voltage provided to gate controlled node); and providing the first reference voltage signal to the first node by a second switch (controlled transistor proved regulated voltage to bitline), wherein a control terminal of the second switch is coupled to the second node (transistor gate coupled o feedback generated control node Siau Fig 5B-5C) for the purpose of allowing a selected bitline to be biased to a desired read voltage despite variations in cell characteristics (feedback controlled biasing maintains the selected bitline at the desired read voltage despite variation in cell current voltage behavior of different memory cells, Siau Fig 5B-5F).
Since Birk and Siau are both from the same field of endeavor (semiconductor memory comprising sense amplifiers), the purpose disclosed by Siau would have been recognized in the pertinent art of Birk.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Siau’s transistor controlled feedback biased read circuitry in the circuit taught by Birk for the purpose of establishing and regulating desired bitline read voltages despite variations in memory cell characteristics.
Claim 19. Birk and Siau teach the method of claim 17, further comprising: providing a second reference voltage signal to a third node according to the by a third switch (controlled memory read circuit provides selected operating voltages through transistor controlled notes, Siau Fig 4A, 5E-5F); storing the data by a memory device (cells coupled to the selected bitlines store data being sensed, Birk [0033-0035], Siau Figs 4A, 5E-5F); and coupling the memory device to the first node by a fourth switch (bitline select access devices selectively coupled the memory array to the bitline read circuit, Siau Fig 4A), wherein a control terminal of the fourth switch is coupled to the third node (bitline select access device is controlled by the corresponding select control node, Siau Fig 4A).
Claim 20. Birk and Siau teach the method of claim 19, wherein generating the first control signal comprises: generating the first control signal based on the second reference voltage signal (the bitline gate bias control condition is generated based on the source read voltage bias together with closed loop feedback from the selected bitline, Siau Fig 5B-5F).
Claims 7, 12-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Birk (Patent Application Publication 2002/0181306) in view of Siau (Patent Application Publication 2016/0254048), further in view of Nautiyal (Patent Application Publication 2004/0130353).
Claim 7. Birk and Siau teach the device of claim 6, but are silent with respect to wherein the second logic unit comprises: a first logic element configured to receive the reference voltage signal and output a third control signal; and a second logic element configured to receive the third control signal and output the second control signal, wherein a control terminal of the fifth switch is configured receive the third control signal.
Nautiyal teaches a first logic element configured to (configured to is functional language) receive the reference voltage signal and output a third control signal; and a second logic element configured to (configured to is functional language) receive the third control signal and output the second control signal, wherein a control terminal of the fifth switch is configured to (configured to is functional language) receive the third control signal (first inverter logic stage generating control output, subsequent logic stage generating further control output, logic output applied to transistor control terminal, Nautiyal Fig 2 [0017-0023]) for the purpose of dynamically controlling states in sense path to suppress noise and improve stability and reliability (Nautiyal Fig 2 [0017-0023]).
Since Birk, Siau and Nautiyal are from the same field of endeavor (semiconductor memory comprising sense amplifiers), the purpose disclosed by Birk and Siau would have been recognized in the pertinent art of Nautiyal.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Nautiyal’s cascaded logic inverter control path with the circuit taught by Nirk and Siau for the purpose of dynamically controlling states in sense path to suppress noise and improve stability and reliability (Nautiyal Fig 2 [0017-0023]).
Claim 12. Birk and Siau teach the device of claim 11, but are silent with respect to further comprising: a sensing device configured to generate a first digital signal and a second digital signal according to the first voltage signal, wherein the feedback device is configured to generate a first control signal and a second control signal based on the first digital signal and the second digital signal, respectively, the first reading circuit and the second reading circuit are configured to receive the first control signal and the second control signal, respectively.
Nautiyal teaches a sensing device configured to (configured to is functional language) generate a first digital signal and a second digital signal according to the first voltage signal, wherein the feedback device is configured to (configured to is functional language) generate a first control signal and a second control signal based on the first digital signal and the second digital signal, respectively, the first reading circuit and the second reading circuit are configured to (configured to is functional language) receive the first control signal and the second control signal, respectively (first and second digital signals at sense nodes SN1 and SN2, respective inverter feedback paths INV1 and INV2 generate corresponding control signals, respective transistor paths receive those control signals, Nautiyal Fig 2 [0017-0018]) for the purpose of controlling sensing paths based on sensed state to reduce noise, evaluate speed, and improve sense amp stability and reliability (Nautiyal Fig 2 [0018-0023]).
Since Birk, Siau and Nautiyal are from the same field of endeavor (semiconductor memory comprising sense amplifiers), the purpose disclosed by Birk and Siau would have been recognized in the pertinent art of Nautiyal.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Nautiyal’s cascaded logic inverter control path with the circuit taught by Nirk and Siau for the purpose of controlling sensing paths based on sensed state to reduce noise, evaluate speed, and improve sense amp stability and reliability (Nautiyal Fig 2 [0018-0023]).
Claim 13. The device of claim 12, wherein the first digital signal and the second digital signal are complemented from each other (latch sense amplifier provides opposing nodes SN1 and SN2 coupled to respective feedback inverter paths, Nautiyal Fig 2).
Claim 14. The device of claim 12, wherein the feedback device comprises: a first logic unit configured to (configured to is functional language) receive a reference voltage signal and the first digital signal and output the first control signal (first inverter feedback path receives one sensed latch state and with Siau’s read voltage bias condition, generates the corresponding transistor control output, Nautiyal Fig 2 [0023], Siau Figs 5B-5F); and a second logic unit configured to (configured to is functional language) receive the reference voltage signal and the second digital signal and output the second control signal (second inverter path received opposite sensed latch state and with Siau’s read bias condition, generated the corresponding control output, Nautiyal Fig 2 [0023], Siau Figs 5B-5F).
Claim 15. The device of claim 14, wherein each of the memory device and the second reading circuit is configured to (configured to is functional language) receive the reference voltage signal (Memory cells are ready under the controlled bitline read condition, Siau Fig 5E-5F. First and second sending precharge circuits use controlled source read voltage arrangement, Siau Fig 5F).
Claim 18. Birk and Siau teach the method of claim 17, but are silent with respect to further comprising: generating a second control signal based on the first voltage signal; inverting the second control signal to generate the first control signal; receiving each of the second control signal and the first control signal by a third switch; and controlling the second switch by the third switch.
Nautiyal teaches generating a second control signal based on the first voltage signal; inverting the second control signal to generate the first control signal; receiving each of the second control signal and the first control signal by a third switch; and controlling the second switch by the third switch (sensed node is supplied to the inverter, inverter generated feedback control output, feedback output controls access transistor state, Nautiyal Fig 2 [0017-0023]) for the purpose of controlling sensing paths based on sensed state to reduce noise, evaluate speed, and improve sense amp stability and reliability (Nautiyal Fig 2 [0018-0023]).
Since Birk, Siau and Nautiyal are from the same field of endeavor (semiconductor memory comprising sense amplifiers), the purpose disclosed by Birk and Siau would have been recognized in the pertinent art of Nautiyal.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Nautiyal’s cascaded logic inverter control path with the circuit taught by Nirk and Siau for the purpose of controlling sensing paths based on sensed state to reduce noise, evaluate speed, and improve sense amp stability and reliability (Nautiyal Fig 2 [0018-0023]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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