DETAILED ACTION
This action is responsive to the following communications: the Application filed on December 23, 2024 and the Provisional application No. 63/617,328 filed on January 3, 2024.
Claims 1-25 are pending. Claims 1, 18 and 25 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 13, 16-18, 20-21 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar et al. (US 20220366999).
Regarding independent claim 1, Kumar et al. disclose a memory device [Fig. 2: 200], comprising:
one or more memory devices [see Fig. 2, para. 27]; and
processing circuitry coupled with the one or more memory devices [see Fig. 2, one or more NAND devices 202 may interface with a NAND interface 204 that interacts with an SSD controller 206, para. 27] and configured to cause the memory device to:
initiate a scan operation for a block of the memory device [the value of a read counter may be used to determine when to check the health of the one or more blocks, and checking health may include performing test reads, para. 41. See Fig. 5, a method 500 for selecting thresholds for counters to determine when to perform test reads, para. 50. The method 500 is performed for a single block as the subject block, para. 65];
perform an access operation on the block based at least in part on one or more operating parameters associated with the memory device [see Fig. 5, the method 500 includes executing read commands 506 that includes incrementing (+1) the counter of a block with respect to which each read command is executed. The method 500 includes evaluating 508 the PEC of the SSD 200, para. 67];
adjust a counter associated with the block based at least in part on performing the access operation [the read disturb algorithm tracks the number of read commands on particular blocks using counters, para. 34. Each block has its own counter, para. 65. Executing read commands 506 includes incrementing (+1) the counter of a block with respect to which each read command is executed, para. 67]; and
perform, as part of the scan operation, a read disturb scan for the block based at least in part on the counter satisfying a threshold [the value of a read counter is used to determine when to check the health of the one or more blocks and that checking health includes test reads, para. 41. The counter for each block is evaluated with respect to the counter threshold for that block, para. 69. If the counter of a block is found to have crossed the counter threshold, then a test read is performed, para. 70], wherein the threshold is associated with a frequency for the scan operation, and wherein the one or more operating parameters comprise the frequency [see Table 2, test read frequencies change based on the number of errors observed from the block and the test read frequency is higher near end of life, para. 62. The next counter threshold is updated by adding a frequency value to the current counter threshold, para. 71].
Regarding claim 3, Kumar et al. disclose wherein the processing circuitry is further configured to cause the memory device to:
perform a test operation on the memory device, the test operation associated with a quantity of errors of the memory device [as the test read of the block is performed, error statistics are gathered, which may include counting the number of occurrences of each bin number reported by the ECC decoder, para. 70], wherein initiating the scan operation is based at least in part on the quantity of errors of the memory device detected during the test operation satisfying a threshold quantity of errors [error statistics are gathered and compared with garbage collection (GC) threshold. If the error statistics are found to meet the GC threshold, then garbage collection is performed for the block, para. 73].
Regarding claim 4, Kumar et al. disclose wherein performing the read disturb scan comprises the processing circuitry configured to cause the memory device to:
scan one or more pages for one or more word lines of the block [the test reads is performed on LSB pages of a block according to the read disturb algorithm, para. 47-48], wherein the one or more pages are scanned based at least in part on a priority rating of the one or more pages [the least significant bit (LSB) of the decoded word is the most likely to be incorrect as a result of read disturb, para. 44. Reading only LSB pages is sufficient because LSB pages are affected first and most significantly, para. 48]; and
identify a quantity of errors associated with voltage thresholds of the one or more pages based at least in part on the scanning [as the test read of the block is performed, error statistics are gathered, which may include counting the number of occurrences of each bin number reported by the ECC decoder, para. 70].
Regarding claim 13, Kumar et al. disclose wherein the processing circuitry is further configured to cause the memory device to:
compare, based at least in part on performing the read disturb scan, a quantity of errors of the block with a threshold quantity of errors [as the test read of the block is performed, error statistics are gathered, and compared with garbage collection (GC) threshold, para. 70-73]; and
fold the block based at least in part on the quantity of errors satisfying the threshold quantity of errors [if the error statistics are found to meet the GC threshold, then garbage collection is performed for the block, para. 73].
Regarding claim 16, Kumar et al. disclose wherein performing the access operation comprises the processing circuitry configured to cause the memory device to:
receive a read command for a page of the block [the SSD controller receives read and write instructions from a host interface implemented on or for a host device, para. 27. In a normal read command operation, data read from the SSD 200 is processed by an error control coding (ECC) decoder, para. 51]; and
perform a read operation for the page of the block based at least in part on receiving the read command [the NAND structure includes pages/wordlines in blocks, para. 30-31. The method 500 includes executing read commands, para. 67].
Regarding claim 17, Kumar et al. disclose wherein the one or more operating parameters comprises a program erase count, or a temperature of the memory device, or both [PEC ranges are used to select tables and test read frequencies, para. 59-62 and 66].
Regarding independent claim 18, Kumar et al. disclose a non-transitory computer-readable medium storing code [para. 16-17], the code comprising instructions executable by one or more processors [para. 19] to:
initiate a scan operation for a block of a memory device [the value of a read counter may be used to determine when to check the health of the one or more blocks, and checking health may include performing test reads, para. 41. See Fig. 5, a method 500 for selecting thresholds for counters to determine when to perform test reads, para. 50. The method 500 is performed for a single block as the subject block, para. 65];
perform an access operation on the block based at least in part on one or more operating parameters associated with the memory device [see Fig. 5, the method 500 includes executing read commands 506 that includes incrementing (+1) the counter of a block with respect to which each read command is executed. The method 500 includes evaluating 508 the PEC of the SSD 200, para. 67];
adjust a counter associated with the block based at least in part on performing the access operation [the read disturb algorithm tracks the number of read commands on particular blocks using counters, para. 34. Each block has its own counter, para. 65. Executing read commands 506 includes incrementing (+1) the counter of a block with respect to which each read command is executed, para. 67]; and
perform, as part of the scan operation, a read disturb scan for the block based at least in part on the counter satisfying a threshold [the value of a read counter is used to determine when to check the health of the one or more blocks and that checking health includes test reads, para. 41. The counter for each block is evaluated with respect to the counter threshold for that block, para. 69. If the counter of a block is found to have crossed the counter threshold, then a test read is performed, para. 70], wherein the threshold is associated with a frequency for the scan operation, and wherein the one or more operating parameters comprise the frequency [see Table 2, test read frequencies change based on the number of errors observed from the block and the test read frequency is higher near end of life, para. 62. The next counter threshold is updated by adding a frequency value to the current counter threshold, para. 71].
Regarding claim 20, Kumar et al. disclose wherein the instructions are further executable by the one or more processors to:
perform a test operation on the memory device, the test operation associated with a quantity of errors of the memory device [as the test read of the block is performed, error statistics are gathered, which may include counting the number of occurrences of each bin number reported by the ECC decoder, para. 70], wherein initiating the scan operation is based at least in part on the quantity of errors of the memory device detected during the test operation satisfying a threshold quantity of errors [error statistics are gathered and compared with garbage collection (GC) threshold. If the error statistics are found to meet the GC threshold, then garbage collection is performed for the block, para. 73].
Regarding claim 21, Kumar et al. disclose wherein the instructions to perform the read disturb scan are executable by the one or more processors to:
scan one or more pages for one or more word lines of the block [the test reads is performed on LSB pages of a block according to the read disturb algorithm, para. 47-48], wherein the one or more pages are scanned based at least in part on a priority rating of the one or more pages [the least significant bit (LSB) of the decoded word is the most likely to be incorrect as a result of read disturb, para. 44. Reading only LSB pages is sufficient because LSB pages are affected first and most significantly, para. 48]; and
identify a quantity of errors associated with voltage thresholds of the one or more pages based at least in part on the scanning [as the test read of the block is performed, error statistics are gathered, which may include counting the number of occurrences of each bin number reported by the ECC decoder, para. 70].
Regarding independent claim 25, Kumar et al. a method [Fig. 5: 500] by a memory device, comprising:
initiating a scan operation for a block of the memory device [the value of a read counter may be used to determine when to check the health of the one or more blocks, and checking health may include performing test reads, para. 41. See Fig. 5, a method 500 for selecting thresholds for counters to determine when to perform test reads, para. 50. The method 500 is performed for a single block as the subject block, para. 65];
performing an access operation on the block based at least in part on one or more operating parameters associated with the memory device [see Fig. 5, the method 500 includes executing read commands 506 that includes incrementing (+1) the counter of a block with respect to which each read command is executed. The method 500 includes evaluating 508 the PEC of the SSD 200, para. 67];
adjusting a counter associated with the block based at least in part on performing the access operation [the read disturb algorithm tracks the number of read commands on particular blocks using counters, para. 34. Each block has its own counter, para. 65. Executing read commands 506 includes incrementing (+1) the counter of a block with respect to which each read command is executed, para. 67]; and
performing, as part of the scan operation, a read disturb scan for the block based at least in part on the counter satisfying a threshold [the value of a read counter is used to determine when to check the health of the one or more blocks and that checking health includes test reads, para. 41. The counter for each block is evaluated with respect to the counter threshold for that block, para. 69. If the counter of a block is found to have crossed the counter threshold, then a test read is performed, para. 70], wherein the threshold is associated with a frequency for the scan operation, and wherein the one or more operating parameters comprise the frequency [see Table 2, test read frequencies change based on the number of errors observed from the block and the test read frequency is higher near end of life, para. 62. The next counter threshold is updated by adding a frequency value to the current counter threshold, para. 71].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 20220366999) as applied to claims 1 and 18 above, in view of Yang et al. (US 20210263821).
Regarding claim 2, Kumar et al. teach the limitation with respect to claim 1.
However, Kumar et al. are silent with respect to wherein the processing circuitry is further configured to cause the memory device to:
compare a temperature of the memory device with a threshold temperature, wherein initiating the scan operation is based at least in part on the temperature of the memory device satisfying the threshold temperature.
Yang et al teach wherein the processing circuitry is further configured to cause the memory device to:
compare a temperature of the memory device with a threshold temperature [the health manager determines that one or more storage blocks span a memory die having an elevated die temperature by comparing a current die temperature to a reference die temperature, such as a die temperature threshold, para. 135], wherein initiating the scan operation is based at least in part on the temperature of the memory device satisfying the threshold temperature [read scan frequency may be adjusted based on a detected cross temperature conditions, based on a temperature scan indicating a rise in temperature for a particular logical erase block, metablock, or die within a metablock, and/or based on a cell threshold voltage distribution (CVD) scan that detects a need to change read levels because the bit error rate is too high at current read levels, para. 21].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yang et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process to include temperature threshold comparison of Yang et al. to improve NAND reliability while maintaining scan efficiency.
Regarding claim 19, Kumar et al. teach the limitation with respect to claim 18.
However, Kumar et al. are silent with respect to wherein the instructions are further executable by the one or more processors to:
compare a temperature of the memory device with a threshold temperature, wherein initiating the scan operation is based at least in part on the temperature of the memory device satisfying the threshold temperature.
Yang et al teach wherein the instructions are further executable by the one or more processors to:
compare a temperature of the memory device with a threshold temperature [the health manager determines that one or more storage blocks span a memory die having an elevated die temperature by comparing a current die temperature to a reference die temperature, such as a die temperature threshold, para. 135], wherein initiating the scan operation is based at least in part on the temperature of the memory device satisfying the threshold temperature [read scan frequency may be adjusted based on a detected cross temperature conditions, based on a temperature scan indicating a rise in temperature for a particular logical erase block, metablock, or die within a metablock, and/or based on a cell threshold voltage distribution (CVD) scan that detects a need to change read levels because the bit error rate is too high at current read levels, para. 21].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yang et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process to include temperature threshold comparison of Yang et al. to improve NAND reliability while maintaining scan efficiency.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 20220366999) as applied to claim 4 above, in view of Parthasarathy et al. (US 20220076757).
Regarding claim 9, Kumar et al. teach the limitation with respect to claim 4.
However, Kumar et al. are silent with respect to wherein the processing circuitry is further configured to cause the memory device to:
select, from among a plurality of word lines of the block, the one or more word lines randomly based at least in part on a second quantity of errors previously detected at the one or more word lines.
Parthasarathy et al. teach select, from among a plurality of word lines of the block, the one or more word lines randomly based at least in part on a second quantity of errors previously detected at the one or more word lines [a read disturb scan of unprogrammed memory cells is performed to determine an extent of read disturb, para. 66. Controller 211 uses an output from an artificial neural network (ANN) (not shown) to determine when to initiate a read disturb scan for a particular memory block. Inputs to the ANN include an error rate associated with reading data from programmed memory cells 252 and/or prior test reads performed for unprogrammed memory cells 250. The error rate is based on a number of bits corrected in data read from a memory block by the error correcting code, para. 52].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process using word line selection techniques as taught by Parthasarathy et al. to better target word lines likely to reveal read disturb degradation while avoiding the cost of scanning every word line.
Regarding claim 10, Kumar et al. teach the limitation with respect to claim 4.
However, Kumar et al. are silent with respect to wherein the processing circuitry is further configured to cause the memory device to:
select, from among a plurality of word lines of the block, the one or more word lines randomly based at least in part on at least one word line of the plurality of word lines of the block being unprogrammed.
Parthasarathy et al. teach select, from among a plurality of word lines of the block, the one or more word lines randomly based at least in part on at least one word line of the plurality of word lines of the block being unprogrammed [in order to determine an extent of read disturb 217 associated with unprogrammed memory cells 250, controller 211 uses read disturb scanner 219 to perform one or more test reads of unprogrammed memory cells 250 to obtain a test result, para. 50].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process using word line selection techniques as taught by Parthasarathy et al. to better target word lines likely to reveal read disturb degradation while avoiding the cost of scanning every word line.
Regarding claim 11, Kumar et al. teach the limitation with respect to claim 4.
However, Kumar et al. are silent with respect to wherein the processing circuitry is further configured to cause the memory device to:
select, from among a plurality of word lines of the block, the one or more word lines randomly based at least in part on the one or more word lines being adjacent to a word line selected during the access operation.
Parthasarathy et al. teach select, from among a plurality of word lines of the block, the one or more word lines randomly based at least in part on the one or more word lines being adjacent to a word line selected during the access operation [see Fig. 2, only a portion of unprogrammed memory cells 250 are selected for performing a test read, para. 54. Wordline 212 is selected for performing the test read because wordline 212 is adjacent to wordline 210, (e.g., the last programmed wordline), para. 55].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process using word line selection techniques as taught by Parthasarathy et al. to better target word lines likely to reveal read disturb degradation while avoiding the cost of scanning every word line.
Regarding claim 12, Kumar et al. teach the limitation with respect to claim 4.
However, Kumar et al. are silent with respect to wherein the processing circuitry is further configured to cause the memory device to:
select, from among a plurality of word lines of the block, the one or more word lines based at least in part on the one or more word lines being maintained in a list of word lines stored at the memory device.
Parthasarathy et al. teach select, from among a plurality of word lines of the block, the one or more word lines based at least in part on the one or more word lines being maintained in a list of word lines stored at the memory device [wordlines that are more susceptible to read disturb are known and are selected for test reading and that respective scores or values that indicate susceptibility to read disturb can be stored in a table in memory for each wordline, set of wordlines, memory block, and/or range of memory blocks. The scores or values may be based on prior performance, operating context, or other data collected by controller 211 and used to generate the score or value that can be used to select wordlines to use for test reading, para. 56].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process using word line selection techniques as taught by Parthasarathy et al. to better target word lines likely to reveal read disturb degradation while avoiding the cost of scanning every word line.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 20220366999) as applied to claim 1 above, in view of K et al. (US 20180350446).
Regarding claim 14, Kumar et al. teach the limitation with respect to claim 1.
Furthermore, Kumar et al. disclose wherein the processing circuitry is further configured to cause the memory device to:
compare, based at least in part on performing the read disturb scan, a quantity of errors of the block with a threshold quantity of errors [as the test read of the block is performed, error statistics are gathered, and compared with garbage collection (GC) threshold, para. 70-73].
However, Kumar et al. are silent with respect to reinitiate the scan operation for a second block of the memory device based at least in part on the quantity of errors failing to satisfy the threshold quantity of errors.
K et al. teach compare, based at least in part on performing the scan operation, a quantity of errors of the block with a threshold quantity of errors; and reinitiate the scan operation for a second block of the memory device based at least in part on the quantity of errors failing to satisfy the threshold quantity of errors [If the page has a fail bit count that satisfies the threshold, the system adds the corresponding block to the read scrub queue, para. 148].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of K et al. to the teaching of Kumar et al. such that applying next block queue process if the page has a fail bit count that satisfies the threshold as taught by K et al. to Kumar et al.’s test read process so that the test read resources are not wasted on blocks that do not meet the error threshold and can instead be applied to another candidate block.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 20220366999) as applied to claim 1 above, in view of Sharifi Tehrani et al. (US 20230039624).
Regarding claim 15, Kumar et al. teach the limitation with respect to claim 1.
However, Kumar et al. are silent with respect to wherein the processing circuitry is further configured to cause the memory device to:
generate a positive random value that is less than or equal to the frequency, wherein the threshold associated with the frequency corresponds to the positive random value.
Sharifi Tehrani et al. teach generate a positive random value that is less than or equal to the frequency, wherein the threshold associated with the frequency corresponds to the positive random value [when implementing a probabilistic read disturb handling scheme, the processing device can select an aggressor in the current set by generating a random number (e.g., a uniform random number) in the range of 1 to N. para. 42. The processing device can compare the value of the counter to the first random number generated to identify the aggressor read operation in the current set, para. 44. N is the dynamic value of operations per set, para. 40].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Sharifi Tehrani et al. to the teaching of Kumar et al. such that modifying Kumar et al.’s test read process with random threshold selection as taught by Sharifi Tehrani et al. to maintain the desired average scan frequency while reducing performance overhead.
Allowable Subject Matter
Claims 5-8 and 22-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 5 and 22, the closest prior art, Kumar et al. (US 20220366999), discloses the test reads is performed on least significant bit (LSB) pages of a block according to the read disturb algorithm [para. 47-48], wherein LSB of the decoded word is the most likely to be incorrect as a result of read disturb [para. 44]. Reading only LSB pages is sufficient because LSB pages are affected first and most significantly [para. 48]. However, Kumar et al. do not teach or suggest the one or more pages are scanned based at least in part on a priority rating of the one or more pages, wherein the priority rating of the one or more pages is based at least in part on a quantity of bits stored in one or more memory cells associated with the one or more word lines.
Thus, there is there is no teaching or suggestion in the prior art of record to provide the recited the one or more pages are scanned based at least in part on a priority rating of the one or more pages, wherein the priority rating of the one or more pages is based at least in part on a quantity of bits stored in one or more memory cells associated with the one or more word lines.
Conclusion
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/DUY H LUONG/ Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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