DETAILED ACTION
This action is responsive to the application filed on 12/24/2024. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 14-16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin, PGPUB No. 2021/0216243.
In regards to claim 1, Shin discloses A memory device (See Fig. 1) comprising: a memory array (See Fig. 1 and [0028 and 0037]: wherein array of memory banks are disclosed) an address generator configured to receive an instruction and a base address of the instruction from a host ([0029, 0037, 0046, 0048, 0050-0051]: wherein an address generator (combination of control logic (element 230) and internal address generator common to the memory banks) receives a command and an address of the command from a host) and sequentially generate target addresses for performing operations of the instruction by sequentially adding offsets to the base address ([0038, 0041, 0046-0048, 0052 and 0060]: wherein sequential target addresses for sequential rows are generated for performing operations of the command by sequentially adding offsets to the address. Wherein in order to sequentially read rows of a bank an address for each row would need to be generated (See Figs. 1-4)) a data register configured to store data values corresponding to one or more of the target addresses ([0033 and 0093]: wherein a data register (interpreted as combination of registers of PIM circuits) stores data values corresponding to target addresses to store data used for calculations) and a processing unit configured to perform one or more of the operations of the instruction based on the data values. ([0041-0042, 0047 and 0053]: wherein calculation logic includes processing in memory circuits to perform one or more operations of the command based on the data values (See Figs. 1-4))
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the electronic device corresponding to the memory device of claim 1. (Note: Fig. 1 discloses an electronic device (element 10))
Claim 20 is similarly rejected on the same basis as claim 1 above as claim 20 is the method corresponding to the memory device of claim 1.
In regards to claim 2, Shin discloses The memory device of claim 1 (see rejection of claim 1 above) wherein the address generator comprises: a counter block configured to generate the offsets ([0036, 0056 and 0073]: wherein offset storage generates offsets) a counter selector configured to control the counter block ([0063]: wherein offset configuration unit controls offset storage) and an address adder configured to generate target memory addresses of the target addresses by adding the offsets to the base address. ([0037, 0047-0048 and 0056]: wherein internal address generator adds offsets to base address)
Claim 16 is similarly rejected on the same basis as claim 2 above as claim 16 is the electronic device corresponding to the memory device of claim 2.
In regards to claim 14, Shin discloses The memory device of claim 1 (see rejection of claim 1 above) wherein the offsets have a predetermined interval. ([0038 and 0060]: wherein sequential addresses are read and generated thus the offsets have a predetermined interval of 1 to read a next row. For example, if first address is base + offset, next sequential address is base +offset +1, then base +offset +2, etc.)
Allowable Subject Matter
Claims 3-13 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 3 filed on 12/24/2024. The prior art of record has not taught either individually or in combination and together with all other claimed features “The memory device of claim 2, wherein the counter block comprises: a column counter group comprising a plurality of column counters; and a row counter group comprising a plurality of row counters” as claimed in claim 3, which includes all limitations of claims 1-2.
The closet prior art of record, Shin discloses a memory device which uses an internal address generator to generate sequential target addresses corresponding to data used in operations processed by processing in memory circuitry; wherein the address generator includes an adder, offset storage to generate offsets and an offset configuration unit to control the offset storage. However, Shin does not disclose an address generator comprising a counter block which comprises a column counter group comprising a plurality of column counters; and a row counter group comprising a plurality of row counters as claimed in claims 1-3. While, Song (PGPUB No. 2022/0351765) generally discloses a PIM device with an address generator including a single counter and Mindru (PGPUB No. 2021/0382820) generally discloses a memory address generator including counters, neither reference discloses “…an address generator comprising a counter block which comprises a column counter group comprising a plurality of column counters; and a row counter group comprising a plurality of row counters” as claimed.
Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claim 17 is similarly allowable for the same reasons as claim 3 above.
Claims 4-7 and 18-19 are dependent upon claims 3 and 17 above and therefore are similarly allowable for the same reasons as claims 3 and 17 above.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 8 filed on 12/24/2024. The prior art of record has not taught either individually or in combination and together with all other claimed features “The memory device of claim 2, wherein the counter selector is configured to receive a first instruction for storing subtiles of a first input feature tile of an input feature in a first register group of the data register and a first base address of the first instruction indicating a starting index of the first register group, and control the counter block to generate offsets of the first base address, the address adder is configured to generate first target addresses of the first register group by adding the offsets of the first base address to the first base address, and the first register group is configured to store the subtiles of the first input feature tile in the first register group based on the first target addresses” which includes all limitations of claims 1-2.
The closet prior art of record, Shin discloses a memory device which uses an internal address generator to generate sequential target addresses corresponding to data used in operations processed by processing in memory circuitry; wherein the address generator includes an adder, offset storage to generate offsets and an offset configuration unit to control the offset storage based on receiving control signals from a host. However, Shin does not disclose “…wherein the counter selector is configured to receive a first instruction for storing subtiles of a first input feature tile of an input feature in a first register group of the data register and a first base address of the first instruction indicating a starting index of the first register group, and control the counter block to generate offsets of the first base address, the address adder is configured to generate first target addresses of the first register group by adding the offsets of the first base address to the first base address, and the first register group is configured to store the subtiles of the first input feature tile in the first register group based on the first target addresses…” as claimed in claim 8, which includes all limitations of claims 1-2.
.
Claims 9-13 are dependent upon claim 8 above and therefore are similarly allowable for the same reasons as claim 8 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Song (PGPUB No. 2022/0351765) generally discloses a PIM device with an address generator including a single counter
Mindru (PGPUB No. 2021/0382820) generally discloses a memory address generator including counters
Kim (PGPUB No. 2020/0035278) generally discloses a non-volatile memory device comprising a sequential address generator
NPL reference “Energy-efficient In-Memory Address Calculation” disclosing an in-memory address calculation accelerator using a shift register
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183