DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 6/12/2026. Claims 1-20 are pending and have been examined. Claims 1, 15 and 20 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 14-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin, PGPUB No. 2021/0216243, and further in view of Zhu, PGPUB No. 2018/0314528.
In regards to claim 1, Shin discloses A memory device (See Fig. 1) comprising: a memory array (See Fig. 1 and [0028 and 0037]: wherein array of memory banks are disclosed) an address generator configured to receive an instruction and a base address of the instruction from a host ([0029, 0037, 0046, 0048, 0050-0051]: wherein an address generator (combination of control logic (element 230) and internal address generator common to the memory banks) receives a command and an address of the command from a host) and sequentially generate target addresses for performing operations of the instruction by sequentially adding offsets to the base address ([0038, 0041, 0046-0048, 0052 and 0060]: wherein sequential target addresses for sequential rows are generated for performing operations of the command by sequentially adding offsets to the address. Wherein in order to sequentially read rows of a bank an address for each row would need to be generated (See Figs. 1-4)) a data register configured to store data values corresponding to one or more of the target addresses ([0033 and 0093]: wherein a data register (interpreted as combination of registers of PIM circuits) stores data values corresponding to target addresses to store data used for calculations) and a processing unit configured to perform one or more of the operations of the instruction based on the data values. ([0041-0042, 0047 and 0053]: wherein calculation logic includes processing in memory circuits to perform one or more operations of the command based on the data values (See Figs. 1-4))
Shin does not disclose the offsets corresponding to count values generated by at least one counter of the address generator.
Zhu discloses offsets corresponding to count values generated by at least one counter of the address generator. ([0032-0034]: wherein cache memory includes a hardware control unit (address generator) which includes a counter to generate offsets corresponding to count values. Wherein the offsets are added to a base address in order to generate target addresses (See Figs. 3-4))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the address generator of the memory device of Shin to include a counter to generate offsets as the address generator of the memory device of Zhu. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (using an address generator, of a memory device, including a counter to generate offsets which are added to a base address to generate target addresses as taught in Zhu) to a known device (memory device including an address generator which adds stored offsets to a base address to generate target addresses as taught in Shin) ready for improvement to yield predictable results (a memory device comprising an address generator including a counter to generate offsets which are added to a base address to generate target addresses) for the benefit of using counters to generate offsets which can free up offset register storage space and reduce configuration code (e.g., reduced instruction overhead) used to update/store offset values (MPEP 2143, Example D).
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the electronic device corresponding to the memory device of claim 1. (Note: Shin Fig. 1 discloses an electronic device (element 10) comprising memory device (element 200))
Claim 20 is similarly rejected on the same basis as claim 1 above as claim 20 is the method corresponding to the memory device of claim 1.
In regards to claim 2, the combination of Shin and Zhu discloses The memory device of claim 1 (see rejection of claim 1 above) wherein the address generator comprises: a counter block configured to generate the offsets (Shin [0036, 0056 and 0073]: wherein offset storage generates offsets| Zhu [0032-0034]) a counter selector configured to control the counter block (Shin [0063]: wherein offset configuration unit controls offset storage| Zhu [0032-0034]) and an address adder configured to generate target memory addresses of the target addresses by adding the offsets to the base address. (Shin [0037, 0047-0048 and 0056]: wherein internal address generator adds offsets to base address| Zhu [0034]: element 430 adds offsets to a base address)
Claim 16 is similarly rejected on the same basis as claim 2 above as claim 16 is the electronic device corresponding to the memory device of claim 2.
In regards to claim 14, the combination of Shin and Zhu discloses The memory device of claim 1 (see rejection of claim 1 above) wherein the offsets have a predetermined interval. (Shin [0038 and 0060]: wherein sequential addresses are read and generated thus the offsets have a predetermined interval of 1 to read a next row. For example, if first address is base + offset, next sequential address is base +offset +1, then base +offset +2, etc.| Zhu [0034]))
Allowable Subject Matter
Claims 3-13 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 3 filed on 12/24/2024. The prior art of record has not taught either individually or in combination and together with all other claimed features “The memory device of claim 2, wherein the counter block comprises: a column counter group comprising a plurality of column counters; and a row counter group comprising a plurality of row counters” as claimed in claim 3, which includes all limitations of claims 1-2.
The closet prior art of record, Shin discloses a memory device which uses an internal address generator to generate sequential target addresses corresponding to data used in operations processed by processing in memory circuitry; wherein the address generator includes an adder, offset storage to generate offsets and an offset configuration unit to control the offset storage. However, Shin does not disclose an address generator comprising a counter block which comprises a column counter group comprising a plurality of column counters; and a row counter group comprising a plurality of row counters as claimed in claims 1-3. While, Song (PGPUB No. 2022/0351765) generally discloses a PIM device with an address generator including a single counter and Mindru (PGPUB No. 2021/0382820) generally discloses a memory address generator including counters, neither reference discloses “…an address generator comprising a counter block which comprises a column counter group comprising a plurality of column counters; and a row counter group comprising a plurality of row counters” as claimed.
Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claim 17 is similarly allowable for the same reasons as claim 3 above.
Claims 4-7 and 18-19 are dependent upon claims 3 and 17 above and therefore are similarly allowable for the same reasons as claims 3 and 17 above.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 8 filed on 12/24/2024. The prior art of record has not taught either individually or in combination and together with all other claimed features “The memory device of claim 2, wherein the counter selector is configured to receive a first instruction for storing subtiles of a first input feature tile of an input feature in a first register group of the data register and a first base address of the first instruction indicating a starting index of the first register group, and control the counter block to generate offsets of the first base address, the address adder is configured to generate first target addresses of the first register group by adding the offsets of the first base address to the first base address, and the first register group is configured to store the subtiles of the first input feature tile in the first register group based on the first target addresses” which includes all limitations of claims 1-2.
The closet prior art of record, Shin discloses a memory device which uses an internal address generator to generate sequential target addresses corresponding to data used in operations processed by processing in memory circuitry; wherein the address generator includes an adder, offset storage to generate offsets and an offset configuration unit to control the offset storage based on receiving control signals from a host. However, Shin does not disclose “…wherein the counter selector is configured to receive a first instruction for storing subtiles of a first input feature tile of an input feature in a first register group of the data register and a first base address of the first instruction indicating a starting index of the first register group, and control the counter block to generate offsets of the first base address, the address adder is configured to generate first target addresses of the first register group by adding the offsets of the first base address to the first base address, and the first register group is configured to store the subtiles of the first input feature tile in the first register group based on the first target addresses…” as claimed in claim 8, which includes all limitations of claims 1-2.
.
Claims 9-13 are dependent upon claim 8 above and therefore are similarly allowable for the same reasons as claim 8 above.
Response to Arguments
Applicant’s arguments, see pages 9-13 of the remarks filed on 6/12/2026, with respect to the rejection(s) of claim(s) 1, 15 and 20 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 103 under Shin and Shu.
Claims 2, 14 and 16 are argued at least based upon their dependencies and thus remain rejected at least based upon their dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Herath, PGPUB No. 2020/0264931 for teaching an address generation unit that calculates a memory address by adding a base address +register offset +bank offset; wherein bank offset is generated by a bank counter
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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