DETAILED ACTION
This action is responsive to the following communications: the Application filed on December 24, 2024 and the Information Disclosure Statements filed on December 24, 2024 and October 20, 2025.
Claims 1-20 are pending. Claims 1, 18 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDSs) filed on December 24, 2024 and October 20, 2025. These IDSs have been considered.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0039], lines 5-6, “memory array 202 that can comprises” should be --memory array 202 that can comprise--.
In paragraph [00130], line 1, “the control circuit applied apply a selected” should be --the control circuit applied a selected--.
In paragraph [00130], line 3, “the bit line This embodiment” should be --the bit line. This embodiment--.
In paragraph [00139], lines 12-13, “one or more voltages pulses” should be --one or more voltage pulses--.
In paragraph [00140], line 12, “the signal VBL_inhibitVt” should be --the signal VBL_inhibit--.
In paragraph [00140], line 20, “SGS/SGSB is the voltage applied to is the voltage applied to source side” should be --SGS/SGSB is the voltage applied to source side--.
In paragraph [00167], lines 11-12, “one or more voltages pulses” should be --one or more voltage pulses--.
In paragraph [00168], lines 10, “one or more voltages pulses” should be --one or more voltage pulses--.
Appropriate correction is required.
Claim Objections
Claim 17-19 is objected to because of the following informalities:
In claim 17, line 2, “a first transfer and a second transfer gate” should be --a first transfer gate and a second transfer gate--.
In claim 18, line 15, “one or more voltages pulses” should be --one or more voltage pulses--.
In claim 19, line 12, “one or more voltages pulses” should be --one or more voltage pulses--.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
In claim 20, the term “means for” is treated as a term that invokes means-plus-function because the limitation used the term “means” followed by functional claim language and the claim itself does not recite sufficient structure for performing the recited function. Therefore, the limitation “means for tightening the common threshold voltage distribution…memory cells” is interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 10, the claim recites “the control circuit is further configured to sense the plurality of non-volatile memory cells to determine whether the non-volatile memory cells are at lower threshold voltages or higher threshold voltages”. The terms “lower threshold voltages” and “higher threshold voltage” are relative terms, and the claim does not recite a reference value, threshold voltage distribution, data state, or other objective criterion relative to which a threshold voltage is determined to be “lower” or “higher”. Therefore, the metes and bounds of the claim are unclear. Claim 11 depends on claim 10 and does not remedy the foregoing deficiency. Accordingly, claim 11 is rejected for the same reason.
With respect to claim 14, the claim recites “the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to tighten the common threshold voltage distribution”. The term “tighten” is a term of degree for which the claim does not provide an objective boundary. It is unclear what degree or type of modification to the common threshold voltage distribution constitutes “tightening” within the scope of the claim. Thus, the boundaries of claim 14 are unclear.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 9-10, 12-13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yun et al. (US 20190385681).
Regarding independent claim 1, Yun et al. disclose a non-volatile storage apparatus [Fig. 1: 100], comprising:
a selected word line [see Fig. 3: the word lines WL1-WL8, para. 45];
bit lines [see Fig. 3: the bit lines BL1 to BL3, para. 45];
a plurality of non-volatile memory cells connected to the selected word line and the bit lines [see Fig. 3, each NAND cell string (e.g., a NAND cell string NS11) may include a plurality of memory cells MC1 to MC8 that connected in common to the first bit line BL1 and connected to corresponding word lines WL1 to WL8, para. 46-49]; and
a control circuit [Fig. 1: 120] connected to the selected word line, the bit lines and the non-volatile memory cells [the control logic 120 may, based on a command CMD, an address ADDR, and a control signal CTRL, output various control signals for programming data to the memory cell array 110, reading out data from the memory cell array 110, or erasing data stored in the memory cell array 110, para. 30];
the control circuit is configured to concurrently:
apply a selected erase voltage to the selected word line [in an erase operation, the row decoder 140 may transmit an erase voltage and a verify voltage to a selected word line, para. 34. A voltage V_WL as a word line erase voltage Vwe applied to the word lines WL during the GIDL erase operation, para. 57],
apply a first erase voltage for a first time duration to a first set of the bit lines [see Fig. 8, the erase voltage V_ERS1 is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 from a second time point t2a until a fourth time point t4a, para. 73-74], and
apply a second erase voltage for a second time duration to a second set of the bit lines [see Fig. 8, the erase voltage V_ERS2 is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 from a second time point t2a until a sixth time point t6a, para. 73-74], the first time duration [Fig. 8: t2a-t4a] is different than the second time duration [Fig. 8: t2a-t6a], the first set of the bit lines [BL1 and BL5] is different than the second set of the bit lines [BL2 and BL6].
Regarding claim 2, Yun et al. disclose wherein:
the first time duration is shorter than the second time duration [see Fig. 8, t2a-t4a is shorter than t2a-t6a].
Regarding claim 3, Yun et al. disclose wherein:
the first erase voltage is equal in magnitude to the second erase voltage [see Fig. 8, the first erase voltage V_ERS1 and the second erase voltage V_ERS2 have a same voltage level (e.g., magnitude), para. 61].
Regarding claim 6, Yun et al. disclose wherein:
the control circuit is configured to apply a first erase voltage for a first time duration to a first set of the bit lines by applying one or more erase voltage pulses of a first time duration at a first voltage magnitude to the first set of the bit lines [see Fig. 8, the erase voltage V_ERS1 is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 from a second time point t2a until a fourth time point t4a, para. 73-74. An erase operation performed through a plurality of erase loops may be referred to as an incremental step pulse erase (ISPE), para. 84]; and
the control circuit is configured to apply a second erase voltage for a second time duration to a second set of the bit lines by applying one or more erase voltage pulses of a second time duration at a second voltage magnitude to the second set of the bit lines [see Fig. 8, the erase voltage V_ERS2 is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 from a second time point t2a until a sixth time point t6a, para. 73-74. An erase operation performed through a plurality of erase loops may be referred to as an incremental step pulse erase (ISPE), para. 84].
Regarding claim 9, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by applying one or more erase voltage pulses at an erase enable voltage magnitude to a first subset of the plurality of non-volatile memory cells connected to the first set of the bit lines and to a second subset of the plurality of non-volatile memory cells connected to the second set of the bit lines [see Fig. 8, at a second time point t2a, an erase voltage V_ERSa may be applied to bit lines included in the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4. In the example embodiment, the erase voltage V_ERSa having application times (or holding times) different from one another may be applied to the first group GP1, the second group GP2, the third group GP3, and the fourth group GP4, respectively, para. 73] such that pulse widths of the erase voltage pulses at the erase enable voltage magnitude are truncated for first subset of the plurality of non-volatile memory cells and pulse widths of the erase voltage pulses at the erase enable voltage magnitude are not truncated for second subset of the plurality of non-volatile memory cells [see Fig. 8, the erase voltage V_ERSa is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 until a fourth time point t4a, while the erase voltage V_ERSa is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 until a sixth time point t6a, para. 74].
Regarding claim 10, Yun et al. disclose wherein:
the control circuit is further configured to sense the plurality of non-volatile memory cells to determine whether the non-volatile memory cells are at lower threshold voltages or higher threshold voltages, the first set of the bit lines are connected to the non-volatile memory cells determined to be at the lower threshold voltages, the second set of the bit lines are connected to the non-volatile memory cells determined to be at the higher threshold voltages [see Fig. 10C, in the first erase loop LOOP1, the same first loop erase voltage V_ERS_L11 is applied to the first group GP1 and the second group GP2. A threshold voltage distribution D_D of memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may be formed at a level lower than the verify voltage Vvfy and the threshold voltage distribution D_C of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be at least partially formed at a level higher than the verify voltage Vvfy according to the first erase loop LOOP1, para. 86].
Regarding claim 12, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to lower threshold voltages of non-volatile memory cells connected to the first set of the bit lines and non-volatile memory cells connected the second set of the bit lines [para. 82-83].
Regarding claim 13, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to partially erase non-volatile memory cells connected to the first set of the bit lines and non-volatile memory cells connected the second set of the bit lines [see Fig. 10C, in the second erase loop LOOP2, after V_ERS_L21 is applied to the first group GP1 and V_ERS_L22 is applied to the second group GP2, the threshold voltage distribution D_D of memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 and the threshold voltage distribution D_C of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 are formed lower than the verify voltage Vvfy and lower than themselves in the first erase loop LOOP1].
Regarding claim 15, Yun et al. disclose wherein:
the plurality of non-volatile memory cells are configured to be programmed to one or more data states [the memory cells included in the memory cell array 110 may be non-volatile memory cells capable of maintaining data stored, para. 28. The control logic 120 may, based on a command CMD, an address ADDR, and a control signal CTRL, output various control signals for programming data to the memory cell array 110, para. 30]; and
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to change data states of the non-volatile memory cells connected to the first set of the bit lines and non-volatile memory cells connected the second set of the bit lines [the control logic 120 performs erasing data stored in the memory cell array 110, para. 30. Because the memory cell array 110 may include at least one of a single level cell block including single level cells (SLC), a multilevel cell block including multilevel cells (MLC), a triple level cell block including triple level cells (TLC), and a quad level cell block including quad level cells (QLC), erasing stored data necessarily changes the cell’s data state].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7-8, 11 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 20190385681) in view of Costa et al. (US 20130279256).
Regarding claim 4, Yun et al. teach the limitations with respect to claim 1.
Furthermore, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by:
applying the first erase voltage to the first set of the bit lines from a first time to a second time lines [see Fig. 8, the erase voltage V_ERS1 is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 from a second time point t2a until a fourth time point t4a, para. 73-74],
applying the second erase voltage to the second set of the bit lines from the first time to the third time [see Fig. 8, the erase voltage V_ERS2 is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 from a second time point t2a until a sixth time point t6a, para. 73-74].
Yun et al. are silent with respect to applying an inhibit voltage to the first set of the bit lines from the second time to a third time.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. so that upon completion of the shorter erase voltage to a first group of bit lines, the first group of bit lines is driven to the inhibit voltage as taught by Costa et al. while the erase voltage remains applied to a second group of bit lines to tighten erase distributions, avoid over-stressing the verified memory cells and prevent deep-erased memory cells [see Costa et al.’s para. 114].
Regarding claim 7, Yun et al. teach the limitations with respect to claim 1.
Furthermore, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to adjust non-volatile memory cells connected to the first set of the bit lines and the second set of the bit lines [the differential erase treatments adjust threshold voltage distribution and reduce differences between different groups, para, 72].
However, Yun et al. are silent with respect to the control circuit is further configured apply an inhibit voltage for the second time duration to a third set of the bit lines concurrently while applying the first erase voltage for the first time duration and applying the second erase voltage for the second time duration in order to inhibit adjustment of the non-volatile memory cells connected to the third set of the bit lines.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95]. The controller maintains inhibited or uninhibited status separately for each subset [para. 116].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. to apply an inhibit voltage to a third group of the bit lines as taught by Costa et al. while applying the first erase voltage to a first group of bit lines and applying the second erase voltage to a second group of bit lines throughout the erase interval to prevent over-erasure of cells not requiring adjustment, thereby improving memory reliability.
Regarding claim 8, Yun et al. in combination with Costa et al. teach the limitations with respect to claim 7.
Furthermore, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by:
applying the first erase voltage to the first set of the bit lines from a first time to a second time [see Fig. 8, the erase voltage V_ERS1 is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 from a second time point t2a until a fourth time point t4a, para. 73-74],
applying the second erase voltage to the second set of the bit lines from the first time to the third time [see Fig. 8, the erase voltage V_ERS2 is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 from a second time point t2a until a sixth time point t6a, para. 73-74].
However, Yun et al. are silent with respect to applying the inhibit voltage to the first set of the bit lines from the second time to a third time, and applying the inhibit voltage to the third set of the bit lines from the first time to the third time.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95]. The controller maintains inhibited or uninhibited status separately for each subset [para. 116].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. so that upon completion of the shorter erase voltage to a first group of bit lines, the first group of bit lines is driven to the inhibit voltage as taught by Costa et al. while the erase voltage remains applied to a second group of bit lines and hold a third group of bit lines at Costa et al.’s inhibit voltage to tighten erase distributions, avoid over-stressing the verified memory cells and prevent deep-erased memory cells [see Costa et al.’s para. 114].
Regarding claim 11, Yun et al. teach the limitations with respect to claim 10.
Furthermore, Yun et al. disclose wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to adjust non-volatile memory cells connected to the first set of the bit lines and the second set of the bit lines [the differential erase treatments adjust threshold voltage distribution and reduce differences between different groups, para, 72].
However, Yun et al. are silent with respect to the control circuit is further configured apply an inhibit voltage to a third set of the bit lines concurrently while applying the first erase voltage for the first time duration and applying the second erase voltage for the second time duration in order to inhibit adjustment of the non-volatile memory cells connected to the third set of the bit lines.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95]. The controller maintains inhibited or uninhibited status separately for each subset [para. 116].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. to apply an inhibit voltage to a third group of the bit lines as taught by Costa et al. while applying the first erase voltage to a first group of bit lines and applying the second erase voltage to a second group of bit lines throughout the erase interval to prevent over-erasure of cells not requiring adjustment, thereby improving memory reliability.
Regarding independent claim 18, Yun et al. disclose a method, comprising:
sensing a set of non-volatile memory cells connected to a selected word line [row decoder 140 selects a word line and page buffer 150 operates as a sense amplifier, para. 34-35] to determine whether the non-volatile memory cells are at lower threshold voltages or higher threshold voltages [see Fig. 10C, in the first erase loop LOOP1, the same first loop erase voltage V_ERS_L11 is applied to the first group GP1 and the second group GP2. A threshold voltage distribution D_D of memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may be formed at a level lower than the verify voltage Vvfy and the threshold voltage distribution D_C of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be at least partially formed at a level higher than the verify voltage Vvfy according to the first erase loop LOOP1, para. 86];
applying a selected erase voltage to the selected word line [in an erase operation, the row decoder 140 may transmit an erase voltage and a verify voltage to a selected word line, para. 34. A voltage V_WL as a word line erase voltage Vwe applied to the word lines WL during the GIDL erase operation, para. 57];
after the sensing, applying one or more erase voltage pulses of a first time duration at a first voltage magnitude to non-volatile memory cells determined to be at the lower threshold voltages in order to lower threshold voltages of the non-volatile memory cells determined to be at the lower threshold voltages [see Fig. 8, the erase voltage V_ERS1 is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 from a second time point t2a until a fourth time point t4a, para. 73-74. See Fig. 10C, in the first erase loop LOOP1, the same first loop erase voltage V_ERS_L11 is applied to the first group GP1 and the second group GP2. A threshold voltage distribution D_D of memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may be formed at a level lower than the verify voltage Vvfy and the threshold voltage distribution D_C of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be at least partially formed at a level higher than the verify voltage Vvfy according to the first erase loop LOOP1, para. 86];
after the sensing, applying one or more erase voltage pulses of a second time duration at the first voltage magnitude to non-volatile memory cells determined to be at the higher threshold voltages in order to lower threshold voltages of the non-volatile memory cells determined to be at the higher threshold voltages [see Fig. 8, the erase voltage V_ERS2 is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 from a second time point t2a until a sixth time point t6a, para. 73-74. See Fig. 10C, in the first erase loop LOOP1, the same first loop erase voltage V_ERS_L11 is applied to the first group GP1 and the second group GP2. A threshold voltage distribution D_D of memory cells connected to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 may be formed at a level lower than the verify voltage Vvfy and the threshold voltage distribution D_C of the memory cells connected to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 may be at least partially formed at a level higher than the verify voltage Vvfy according to the first erase loop LOOP1, para. 86], the first time duration [Fig. 8: t2a-t4a] is different than the second time duration [Fig. 8: t2a-t6a].
However, Yun et al. are silent with respect to applying one or more voltages pulses at an inhibit voltage to other non-volatile memory cells connected to the selected word line that are to be inhibited from changing threshold voltage.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95]. The controller maintains inhibited or uninhibited status separately for each subset [para. 116].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. to apply an inhibit voltage to a third group of the bit lines as taught by Costa et al. while applying the first erase voltage to a first group of bit lines and applying the second erase voltage to a second group of bit lines throughout the erase interval to prevent over-erasure of cells not requiring adjustment, thereby improving memory reliability.
Regarding claim 19, Yun et al. in combination with Costa et al. teach the limitations with respect to claim 18.
Furthermore, Yun et al. disclose wherein:
the applying one or more erase voltage pulses of a first time duration at a first voltage magnitude to non-volatile memory cells determined to be at the lower threshold voltages comprises applying an erase enable voltage to non-volatile memory cells determined to be at the lower threshold voltages from a first time to a second time [see Fig. 8, the erase voltage V_ERS1 is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 from a second time point t2a until a fourth time point t4a, para. 73-74];
the applying one or more erase voltage pulses of a second time duration at the first voltage magnitude to non-volatile memory cells determined to be at the higher threshold voltages comprises applying the erase enable voltage to the non-volatile memory cells determined to be at the higher threshold voltages from the first time to the third time [see Fig. 8, the erase voltage V_ERS2 is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 from a second time point t2a until a sixth time point t6a, para. 73-74. The erase voltage V_ERS1 equals to V_ERS2].
However, Yun et al. are silent with respect to applying the inhibit voltage to non-volatile memory cells determined to be at the lower threshold voltages from the second time to a third time and the applying one or more voltages pulses at a third voltage magnitude to other non-volatile memory cells comprises applying the inhibit voltage to the other non-volatile memory cells from the first time to the third time.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95]. The controller maintains inhibited or uninhibited status separately for each subset [para. 116].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. so that upon completion of the shorter erase voltage to a first group of bit lines, the first group of bit lines is driven to the inhibit voltage as taught by Costa et al. while the erase voltage remains applied to a second group of bit lines and hold a third group of bit lines at Costa et al.’s inhibit voltage to tighten erase distributions, avoid over-stressing the verified memory cells and prevent deep-erased memory cells [see Costa et al.’s para. 114].
Regarding independent claim 20, Yun et al. disclose a non-volatile storage apparatus [Fig. 1: 100], comprising:
a selected word line [see Fig. 3: the word lines WL1-WL8, para. 45];
bit lines [see Fig. 3: the bit lines BL1 to BL3, para. 45];
a plurality of non-volatile memory cells connected to the selected word line and the bit lines [see Fig. 3, each NAND cell string (e.g., a NAND cell string NS11) may include a plurality of memory cells MC1 to MC8 that connected in common to the first bit line BL1 and connected to corresponding word lines WL1 to WL8, para. 46-49], the plurality of non-volatile memory cells are configured to be programmed to a common threshold voltage distribution [Yun et al. teach SLC, MLC, TLC, and QLC cells capable of being programmed to data state distribution, para. 29]; and
means for tightening the common threshold voltage distribution by applying one or more erase voltage pulses to a first subset of the plurality of non-volatile memory cells such that pulse widths of the erase voltage pulses at an erase enable voltage magnitude are truncated for non-volatile memory cells of the first subset with lower threshold voltages and pulse widths of the erase voltage pulses at the erase enable voltage magnitude are not truncated for non-volatile memory cells of the first subset with higher threshold voltages [see Fig. 8, the erase voltage V_ERSa is applied to the first bit line BL1 and the fifth bit line BL5 included in the first group GP1 until a fourth time point t4a, while the erase voltage V_ERSa is applied to the second bit line BL2 and the sixth bit line BL6 included in the second group GP2 until a sixth time point t6a, para. 74].
However, Yun et al. are silent with respect to while not adjusting threshold voltages of a second subset of the plurality of non-volatile memory cells.
Costa et al. teach a BL subset can be independently inhibited from being erased by setting a voltage of the BL to a sufficiently low level which inhibits erase [para. 66]. Costa et al. further teach one bit line subset can be inhibited while another bit line subset remains uninhibited and receives a sufficiently high erase voltage [para. 94-95]. The controller maintains inhibited or uninhibited status separately for each subset [para. 116].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Costa et al. to the teaching of Yun et al. such that modifying the erase control circuit of Yun et al. to apply an inhibit voltage to a third group of the bit lines as taught by Costa et al. while applying the first erase voltage to a first group of bit lines and applying the second erase voltage to a second group of bit lines throughout the erase interval to prevent over-erasure of cells not requiring adjustment, thereby improving memory reliability.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 20190385681) in view of Banerjee et al. (US 20200395087).
Regarding claim 5, Yun et al. teach the limitations with respect to claim 1.
However, Yun et al. are silent with respect to wherein:
the first erase voltage and the second erase voltage are derived from a same charge pump.
Banerjee et al. disclose soft erase circuit 1722 may be combined with erase circuits (e.g. using common components such as charge pumps to generate soft erase voltage pulses and erase voltage pulses) and may be configured to erase and soft erase blocks at different times [para. 141].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Banerjee et al. to the teaching of Yun et al. such that implementing voltage generator 130 of Yun et al. using a single charge pump as taught by Banerjee et al because charge pumps are a known mechanism for generate erase voltages. This modification would predictably reduce circuit area and power consumption.
Allowable Subject Matter
Claims 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 16, there is no teaching or suggestion in the prior art of record to provide the recited wherein the control circuit include sensing circuits and bit line interface circuits; the bit line interface circuits each connect one sensing circuit and one or more voltage sources to one bit line; the control circuit is configured apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by: applying an erase enable voltage to the bit line interface circuits, configuring the bit line interface circuits to pass the erase enable voltage to respective bit lines at a first time, configuring the bit line interface circuits to float all of the bit lines at a second time after the first time, configuring bit line interface circuits connected to the first set of the bit lines to provide a path to discharge the respective connected bit lines at the second time, and configuring bit line interface circuits connected to the second set of the bit lines to maintain respective connected bit lines at the erase enable voltage until a third time that is after the second time.
With respect to claim 17, there is no teaching or suggestion in the prior art of record to provide the recited wherein the control circuit comprises a charge pump connected to a first transfer and a second transfer gate; the control circuit is configured apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by: applying a first gate voltage to the first transfer gate at a first time until a second time, applying a second gate voltage to the first transfer gate at the second time until a third time, and applying the first gate voltage to the second transfer gate at the first time until the third time.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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