Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 27.
b. Claims 1-28 are pending on the application.
Drawings
2. The drawings were received on 12/26/2024 and 01/25/2025. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 11/06/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 09/19/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 05/05/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 04/15/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claim 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,699,695 B2 to Lee. (hereafter Lee) in view of US 2012/0099389 A1 to Park et al. (hereafter Park et al).
Regarding independent claim 27, Lee discloses a multi-threaded dynamic random access memory (MTDRAM) processor system (a semiconductor memory device 100A, Fig. 1A-1C, column 3, lines 43-45) comprising:
a first integrated circuit chip (an integrated circuit 20 may include a first integrated circuit 20-1, Fig. 1A) comprising at least 2048 processor blocks arranged in a first array (the first integrated circuit 20-1 may include a logic circuit including a logic cells 21-1, Fig. 1A, column 3, lines 65-67); and
a second integrated circuit chip (an integrated circuit 20 may include a second integrated circuit 20-2, Fig. 1A) comprising at least 2048 independent dynamic random access memory (DRAM) unit cells arranged in a second array (the second integrated circuit 20-2 may include a logic circuit including a logic cells 21-2, Fig. 1A, column 3, lines 65-67),
wherein each of the at least 2048 processor blocks (the first integrated circuit 20-1 include the logic cells 21-1) is coupled to a corresponding one of the at least 2048 independent DRAM unit cells of the second array of DRAM unit cells (the second integrated circuit 20-2 include the logic cells 21-2) by through silicon via (TSV) structures (a TSV 40, Fig. 1A)(the first TSV area 40R1 and the second area 40R2 are disposed between the first integrated circuit 20-1 and the second integrated circuit 20-2, Fig. 1A, column 4, lines 61-65).
Lee does not expressly disclose the second integrated circuit chip comprising independent DRAM unit cells.
Park et al teaches a memory management chip 1100 directly can control each of DRAM chip 1200-1….1200-1 (Fig. 1, column 3, paragraph 0049).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filling data of this application, to combine the DRAM device of Part et al, which is necessary to convert dram device into a readable state, with dram of Lee, with a reasonable expectation of success. Both inventions are well know in the filed of managing partially filled dram and the combination of known inventions with predictable results is obvious and not patentable.
Regarding dependent Claim 28, Lee discloses the MTDRAM processor system, further comprising: a third integrated circuit chip (Lee discloses the first integrated circuit 20-1, the second integrated circuit 20-1 and can also add the third integrated circuit that are spaced apart from each other or thorough understanding of the inventive concept to those of ordinary skill in the art) comprising at least 2048 independent DRAM unit cells arranged in a third array, wherein each of the at least 2048 processor blocks is coupled to a corresponding one of the at least 2048 independent DRAM unit cells of the third array by through silicon via (TSV) structures (the first TSV area 40R1 and the second area 40R2 are disposed between the first integrated circuit 20-1 and the second integrated circuit 20-2, Fig. 1A, column 4, lines 61-65).
Allowable Subject Matter
5. Claims 1-26 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 1: there is no teaching, suggestion, or motivation for combination in the prior art to “each of the unit cells comprises: a first plurality of global bit line sets, wherein each of the first plurality of global bit line sets is coupled to a corresponding one of the first plurality of columns of DRAM sub-arrays through the primary single-ended sense amplifier circuits coupled to the DRAM sub-arrays in the corresponding one of the first plurality of columns of DRAM sub-arrays; a first multiplexer circuit coupled to each of the first plurality of global bit line sets, wherein the first multiplexer circuit selectively couples one of the first plurality of global bit line sets to a first set of global input/output lines; a first secondary sense amplifier circuit coupled to the first set of global input/output lines; and a first set of through silicon vias coupled to the first secondary sense amplifier circuit.” in an integrated circuit chip as claimed in the independent claim 1. Claims 2-26 are also allowed because of their dependency on claim 1.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al (US. 12,250,807) discloses semiconductor device using different types of through silicon vias.
Ganguly et al (US. 2022/0326958 A1) discloses look-up containing processor in memory cluster for data intensive application.
Lee et al (US. 6,570,781 B1) discloses logic process dram.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights