4 pending office actions • 0 art units • 3 examiners • 0 of 4 (0%) have an AI response strategy ready • 9 patents granted in the last 365 days
Atomera Incorporated is currently managing 4 pending office actions. These matters are distributed among 3 distinct examiners, which indicates a concentration of the workload. Pho M Luu is identified as the busiest examiner for this portfolio, currently overseeing 2 pending office actions. This means that Pho M Luu is responsible for 2 of the 4 total pending actions, making his individual examination style a significant factor in the portfolio's overall progress.
The data reports 0 distinct art units for these 4 pending office actions. This suggests that the administrative classification of these matters is highly focused or falls outside the standard art unit groupings listed. With 3 distinct examiners involved, the company must navigate different perspectives, even with the concentration under Pho M Luu. Practitioners should prioritize understanding the specific requirements of the 3 distinct examiners to ensure that the 4 pending office actions are addressed effectively across the various individual examination styles encountered. The presence of 2 actions under Pho M Luu provides a point of consolidation in this workload, while the 0 distinct art units indicate a unique administrative profile.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (75%) |
| §102 only | 1 (25%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| LUU, PHO M | 2 | 96.9% | +3.3% |
| SNOW, COLLEEN ERIN | 1 | 79.1% | +11.2% |
| MANDALA, MICHELLE | 1 | 91.0% | +7.9% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19002251 | Integrated Circuit Chip Including Arrays Of Multi-Threaded Dynamic Random Access Memory Unit Cells | LUU, PHO M | — |
| 19002273 | Interconnect Structure For An Array Of Multi-Threaded Dynamic Random Access Memory Systems | LUU, PHO M | — |
| 18654141 | SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS | MANDALA, MICHELLE | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18654178 | METHODS FOR MAKING SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS | SNOW, COLLEEN ERIN | — |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19002251 | Integrated Circuit Chip Including Arrays Of Multi-Threaded Dynamic Random Access Memory Unit Cells | LUU, PHO M | — | §103 | Non-Final OA | — | Pending | Dec 26, 2024 |
| 19002273 | Interconnect Structure For An Array Of Multi-Threaded Dynamic Random Access Memory Systems | LUU, PHO M | — | §102 | Non-Final OA | — | Pending | Dec 26, 2024 |
| 18654178 | METHODS FOR MAKING SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS | SNOW, COLLEEN ERIN | — | §103 | Non-Final OA | — | Pending | May 03, 2024 |
| 18654141 | SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS | MANDALA, MICHELLE | — | §103 | Non-Final OA | — | Pending | May 03, 2024 |
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