Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 18.
b. Claims 1-29 are pending on the application.
Drawings
2. The drawings were received on 12/26/2024. These drawings are reviewed and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/26/2026. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/24/2026. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 11/06/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 10/08/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 09/19/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 05/05/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 04/15/2025. The information disclosed therein was considered.
Specification
4. The disclosure is objected to because of the following informalities:
In the first paragraph of the specification, the status of the continuation-in-part of U.S. Application No. 18/399,579 should be updated; namely, it has matured into U.S. Patent No. 12,712,011. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 18, 21 and 23-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0270422 A1 to Grinberg et al. (hereafter Grinberg et al).
Regarding Independent Claim 18, Grinberg et al in Figures 1-4 are directly disclosed an integrated circuit chip (an array sensor system 10, Figures 1-4) comprising:
a plurality of processor blocks (a processor 52, Fig. 3) arranged in an array (a memory 54, Fig. 3) having a plurality of rows and columns (the memory 54 includes a plurality of memory array, each of memory array contain a plurality of memory cell coupled to the row and column), wherein each of the processor blocks includes a corresponding processor nexus (a logic block 60, Fig. 3, which contain the processor 52 is in communication with a logic 60); wherein each row of the plurality of rows of processor blocks (the processor 52 configured to execute instruction stored in memory 54 or to read/write data to the memory 54, Fig. 3, paragraph 0023) comprises:
a first set (a first array set 102, Fig. 2) of horizontal interconnect structures coupling the processor nexuses within the row, enabling communication between the processor nexuses within the row (for example, the selection circuit for a first array 102 includes a row selection circuit 120 and a column selection circuit 130, paragraph 0021);
a second set (a second array set 104, Fig. 2) of horizontal interconnect structures coupling the processor nexuses within the row, enabling communication between the processor nexuses within the row (for example, the selection circuit for a second array 104 includes a row selection circuit 121 and a column selection circuit 131, paragraph 0021); and
a horizontal transport controller (a controller 30) coupled to the first (the first array set 102) and second sets (the second array set 104) of horizontal interconnect structures (the controller 30 uses the electrical signal 16 incorporated into the optical sensor 50, where are the optical sensor 50 includes the first array set 102 and the second array set 104, Figs. 1-2), wherein the horizontal transport controller (the controller 30) includes an interface that enables communication between the processor nexuses within the row and one or more devices external to the integrated circuit chip (the controller 30 uses the electrical signal 16 incorporated into the optical sensor 50, where are the optical sensor 50 includes the first array set 102 and the second array set 104, see at least in Figs. 1-3, paragraph 0017-0027 and the related disclosures).
Regarding dependent Claim 21, Grinberg et al in Figures 1-4 are directly disclosed an integrated circuit chip (an array sensor system 10, Figures 1-4), wherein the first (the first array set 102) and second sets (the second array set 104) of horizontal interconnect structures each include a plurality of bus lines (input line 152, 153) which are fabricated in one or more metal layers of the integrated circuit chip (an input lines 152, 153 which are fabricated in optical sensor 50, Fig. 2).
Regarding dependent Claim 23, Grinberg et al in Figures 1-4 are directly disclosed an integrated circuit chip (an array sensor system 10, Figures 1-4), wherein the horizontal transport controller (the controller 30) within each row is centrally located within the row (the controller 30 use the electrical signal 16 to the applicant and may be incorporated into the optical sensor 50, Fig. 1, paragraph 0018).
Regarding dependent Claim 24, Grinberg et al in Figures 1-4 are directly disclosed an integrated circuit chip (an array sensor system 10, Figures 1-4), wherein each of the horizontal transport controllers (the controller 30) is located within a first pair of columns of the plurality of columns of processor blocks (the controller 30 use as perform the processor).
Allowable Subject Matter
6. Claims 19-20, 22 and 25-29, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respect to dependent claims 19-20, the prior art fails to teach or suggest the claimed limitations, namely, the first set of horizontal interconnect structures within each row is located along an upper edge of the row, and the second set of horizontal interconnect structures within each row is located along a lower edge of the row, wherein the upper edge of the row is opposite the lower edge of the row, wherein the processor blocks within each row of the plurality of rows of processor blocks further comprise a plurality of through silicon vias (TSVs), wherein these plurality of TSVs are located between the first and second sets of horizontal interconnect structures of the row.
With respect to dependent claim 22, the prior art fails to teach or suggest the claimed limitations, namely, the first and second sets of horizontal interconnect structures within each of the rows are divided into a plurality of segments, with repeaters coupling the plurality of segments, thereby avoiding direct long distance signal transmission across the entire integrated circuit chip.
With respect to dependent claims 25-29, the prior art fails to teach or suggest the claimed limitations, namely, each of the processor blocks in a first plurality of columns of the plurality of columns of processor blocks further comprises a local vertical transport controller coupled to the corresponding processor nexus of the processor block, wherein each local vertical transport controller includes an interface that enables communication between a corresponding subset of the local vertical transport controllers through a corresponding local vertical communication path external to the integrated circuit chip, wherein a first subset of the processor blocks in each of the first plurality of columns further comprise a regional vertical transport controller, wherein each regional vertical transport controller includes an interface that enables connections to a pair of the local vertical communication paths, and enables communication with another regional vertical transport controller through a corresponding regional vertical communication path external to the integrated circuit chip.
7. Claims 1-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 1: there is no teaching, suggestion, or motivation for combination in the prior art to “a plurality of dynamic random access memory (DRAM) chips, each comprising a plurality of independent DRAM unit cells arranged in a plurality of rows and columns, wherein each of the processor blocks of the controller chip is coupled to a corresponding DRAM unit cell in each of the DRAM chips; a plurality of communication control chips coupled to the array of stacked MTDRAM processor systems; a plurality of power management chips coupled to the plurality of communication control chips and the array of stacked MTDRAM processor systems; a plurality of high-speed communication links coupled to the plurality of communication control chips; and an interconnect structure that includes a silicon substrate with a plurality of patterned metal interconnect layers formed thereon, wherein the array of MTDRAM processor systems, the plurality of communication control chips, the plurality of power management chips and the plurality of high-speed communication links of the arrayed processor system are mounted on, and are interconnected by, the interconnect structure” in a as claimed in the independent claim 1. Claims 2-17 are also allowed because of their dependency on claim 1.
Conclusion
Examiner's note: Examiner has cited columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested by the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kirsch (US. 7,454,593 B2) discloses row and column enable signal activation of processing array element with interconnection logic to simulate bus effect.
Zheng (US. 11,822,617 B2) discloses apparatus and method for matrix multiplication using processing-in-memory.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights